State identification problems for input/output transition systems

Author(s):  
Saddek Bensalem ◽  
Moez Krichen ◽  
Stavros Tripakis
Author(s):  
Ivo Krka ◽  
Nicolás D’Ippolito ◽  
Nenad Medvidović ◽  
Sebastián Uchitel

2015 ◽  
pp. 939-961
Author(s):  
Pramila Mouttappa ◽  
Stephane Maag ◽  
Ana Cavalli

Testing embedded systems to find errors and to validate that the implemented system as per the specifications and requirements has become an important part of the system design. The research community has proposed several formal approaches these last years, but most of them only consider the control portion of the protocol, neglecting the data portions, or are confronted with an overloaded amount of data values to consider. In this chapter, the authors present a novel approach to model protocol properties of embedded application in terms of Input-Output Symbolic Transition Systems (IOSTS) and show how they can be tested on real execution traces taking into account the data and control portions. These properties can be designed to test the conformance of a protocol as well as security aspects. A parametric trace slicing approach is presented to match trace and property. This chapter is illustrated by an application to a set of real execution traces extracted from a real automotive Bluetooth framework with functional and security properties.


2008 ◽  
Vol 78 (1) ◽  
Author(s):  
Y. Ishida ◽  
T. Hashimoto ◽  
M. Horibe ◽  
A. Hayashi

2020 ◽  
Vol 27 (4) ◽  
pp. 376-395
Author(s):  
Aleksandr Sergeevich Tvardovskii ◽  
Nina Vladimirovna Yevtushenko

State identification is the well-known problem in the theory of Finite State Machines (FSM) where homing sequences (HS) are used for the identification of a current FSM state, and this fact is widely used in the area of software and hardware testing and verification. For various kinds of FSMs, such as partial, complete, deterministic, non-deterministic, there exist sufficient and necessary conditions for the existence ofpreset and adaptive HS and algorithms for their derivation. Nowadays timed aspects become very important for hardware and software systems and for this reason classical FSMs are extended by clock variables. In this work, we address the problem of checking the existence and derivation of homing sequences for FSMs with timed guards and show that the length estimation for timed homing sequence coincides with that for untimed FSM. The investigation is based on the FSM abstraction of a Timed FSM, i.e. on a classical FSM which describes behavior of corresponding TFSM and inherits some of its properties. When solving state identification problems for timed FSMs, the existing FSM abstraction is properly optimized.


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