Research on intelligent scenic security early warning platform based on high resolution image: real scene linkage and real-time LBS

This paper presents FPGA implementations of image filtering and image averaging – two widely applied image preprocessing algorithms. The implementations are targeted for real time processing of high frame rate and high resolution image streams. The developed implementations are evaluated in terms of resource usage, power consumption, and achievable frame rates. For the evaluation, Microsemi’s Smartfusion2 Advanced Development Kit is used. It includes a SmartFusion2 M2S150 SoC FPGA. The performance of the developed implementation of image filtering algorithm is compared to a solution provided by MATLAB’s Vision HDL Toolbox, which is evaluated on the same platform. The performance of the developed implementations are also compared with FPGA implementations found in existing publications, although those are evaluated on different FPGA platforms. Difficulties with performance comparison between implementations on different platforms are addressed and limitations of processing image streams with FPGA platforms discussed.

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A reconfigurable coprocessor for high-resolution image filtering in real time

10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 ◽

10.1109/icecs.2003.1302009 ◽

2004 ◽

Cited By ~ 6

Author(s):

I.S. Uzun ◽

A. Amira ◽

F. Bensaali

Keyword(s):

High Resolution ◽

Real Time ◽

Image Filtering ◽

Resolution Image ◽

High Resolution Image

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A Real-Time Learning-Based Super-Resolution System on FPGA

Parallel Processing Letters ◽

10.1142/s0129626420500115 ◽

2020 ◽

Vol 30 (04) ◽

pp. 2050011

Author(s):

Daolu Zha ◽

Xi Jin ◽

Rui Shang ◽

Pengfei Yang

Keyword(s):

High Resolution ◽

Image Quality ◽

Real Time ◽

Feature Learning ◽

Super Resolution ◽

Learning Stage ◽

Resolution Image ◽

High Resolution Image ◽

Image Prediction ◽

Regression Functions

This paper proposes a real-time super-resolution (SR) system. The proposed system performs a fast SR algorithm that generates a high-resolution image from a low-resolution image using direct regression functions with an up-scaling factor of 2. This algorithm contained two processes: feature learning and SR image prediction. The feature learning stage is performed offline, in which several regression functions were trained. The SR image prediction stage is implemented on the proposed system to generate high-resolution image patches. The system implemented on a Xilinx Virtex 7 field-programmable gate array achieves output resolution of [Formula: see text] (UHD) at 85 fps and 700Mpixels/s throughput. Structure similarity (SSIM) is measured for image quality. Experimental results show that the proposed system provides high image quality for real-time applications. And the proposed system possesses high scalability for resolution.

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