DISJOINT-PATHS AND FAULT-TOLERANT ROUTING ON RECURSIVE DUAL-NET

2011 ◽  
Vol 22 (05) ◽  
pp. 1001-1018 ◽  
Author(s):  
YAMIN LI ◽  
SHIETUNG PENG ◽  
WANMING CHU
Keyword(s):  
Fault Tolerant ◽  
Interconnection Network ◽  
Parallel Computers ◽  
Efficient Algorithms ◽  
Disjoint Paths ◽  
Node Degree ◽  
Huge Number ◽  
Critical Issues ◽  
Base Network ◽  
Short Diameter

The recursive dual-net is a newly proposed interconnection network for massive parallel computers. The recursive dual-net is based on recursive dual-construction of a symmetric base network. A k-level dual-construction for k > 0 creates a network containing (2n0)2k/2 nodes with node-degree d0 + k, where n0 and d0 are the number of nodes and the node-degree of the base network, respectively. The recursive dual-net is node and edge symmetric and can contain huge number of nodes with small node-degree and short diameter. Disjoint-paths routing and fault-tolerant routing are fundamental and critical issues for the performance of an interconnection network. In this paper, we propose efficient algorithms for disjoint-paths and fault-tolerant routings on the recursive dual-net.

scholarly journals Fault-Tolerant Path-Embedding of Twisted Hypercube-Like Networks (THLNs)

Mathematics ◽  
2019 ◽  
Vol 7 (11) ◽  
pp. 1066
Author(s):  
Huifeng Zhang ◽  
Xirong Xu ◽  
Qiang Zhang ◽  
Yuansheng Yang
Keyword(s):  
Topological Structure ◽  
Large Scale ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Graph Embedding ◽  
Linear Arrays ◽  
Critical Issues ◽  
Vertex Set ◽  
Network Operation ◽  
Host Graph

It is known widely that an interconnection network can be denoted by a graph G = ( V , E ) , where V denotes the vertex set and E denotes the edge set. Investigating structures of G is necessary to design a suitable topological structure of interconnection network. One of the critical issues in evaluating an interconnection network is graph embedding, which concerns whether a host graph contains a guest graph as its subgraph. Linear arrays (i.e., paths) and rings (i.e., cycles) are two ordinary guest graphs (or basic networks) for parallel and distributed computation. In the process of large-scale interconnection network operation, it is inevitable that various errors may occur at nodes and edges. It is significant to find an embedding of a guest graph into a host graph where all faulty nodes and edges have been removed. This is named as fault-tolerant embedding. The twisted hypercube-like networks ( T H L N s ) contain several important hypercube variants. This paper is concerned with the fault-tolerant path-embedding of n-dimensional (n-D) T H L N s . Let G n be an n-D T H L N and F be a subset of V ( G n ) ∪ E ( G n ) with | F | ≤ n - 2 . We show that for two different arbitrary correct vertices u and v, there is a faultless path P u v of every length l with 2 n - 1 - 1 ≤ l ≤ 2 n - f v - 1 - α , where α = 0 if vertices u and v form a normal vertex-pair and α = 1 if vertices u and v form a weak vertex-pair in G n - F ( n ≥ 5 ).

THE CUBE-OF-RINGS INTERCONNECTION NETWORK

1998 ◽  
Vol 09 (01) ◽  
pp. 25-37 ◽  
Author(s):  
THOMAS J. CORTINA ◽  
ZHIWEI XU
Keyword(s):  
Graph Theory ◽  
Interconnection Networks ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Routing Algorithm ◽  
Parallel Computers ◽  
Closed Form Expression ◽  
Form Expression ◽  
Graph Theoretic ◽  
Basic Graph

We present a family of interconnection networks named the Cube-Of-Rings (COR) networks along with their basic graph-theoretic properties. Aspects of group graph theory are used to show the COR networks are symmetric and optimally fault tolerant. We present a closed-form expression of the diameter and optimal one-to-one routing algorithm for any member of the COR family. We also discuss the suitability of the COR networks as the interconnection network of scalable parallel computers.

scholarly journals Hierarchical Hexagon: A New Fault-Tolerant Interconnection Network for Parallel Systems

2021 ◽  
Vol 21 (1) ◽  
pp. 32-49
Author(s):  
Laxminath Tripathy ◽  
Chita Ranjan Tripathy
Keyword(s):  
Fault Tolerance ◽  
Hamiltonian Cycle ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Parallel Systems ◽  
Node Degree ◽  
Topological Parameters ◽  
Massively Parallel Systems ◽  
Network Cost ◽  
Hypercube Networks

Abstract A new interconnection network topology called Hierarchical Hexagon HH(n) is proposed for massively parallel systems. The new network uses a hexagon as the primary building block and grows hierarchically. Our proposed network is shown to be superior to the star based and the hypercube networks, with respect to node degree, diameter, network cost, and fault tolerance. We thoroughly analyze different topological parameters of the proposed topology including fault tolerance routing and embedding Hamiltonian cycle.

Fault-Tolerant Maximal Local-Connectivity on Cayley Graphs Generated by Transpositions

2019 ◽  
Vol 30 (08) ◽  
pp. 1301-1315 ◽  
Author(s):  
Liqiong Xu ◽  
Shuming Zhou ◽  
Weihua Yang
Keyword(s):  
Fault Tolerance ◽  
Interconnection Networks ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Cayley Graphs ◽  
Disjoint Paths ◽  
Local Connectivity ◽  
Communication Links ◽  
Restricted Condition ◽  
Vertex Disjoint

An interconnection network is usually modeled as a graph, in which vertices and edges correspond to processors and communication links, respectively. Connectivity is an important metric for fault tolerance of interconnection networks. A graph [Formula: see text] is said to be maximally local-connected if each pair of vertices [Formula: see text] and [Formula: see text] are connected by [Formula: see text] vertex-disjoint paths. In this paper, we show that Cayley graphs generated by [Formula: see text]([Formula: see text]) transpositions are [Formula: see text]-fault-tolerant maximally local-connected and are also [Formula: see text]-fault-tolerant one-to-many maximally local-connected if their corresponding transposition generating graphs have a triangle, [Formula: see text]-fault-tolerant one-to-many maximally local-connected if their corresponding transposition generating graphs have no triangles. Furthermore, under the restricted condition that each vertex has at least two fault-free adjacent vertices, Cayley graphs generated by [Formula: see text]([Formula: see text]) transpositions are [Formula: see text]-fault-tolerant maximally local-connected if their corresponding transposition generating graphs have no triangles.

Design of Fault Tolerant Shuffle Exchange Gamma Interconnection Network Layouts

2017 ◽  
Vol 17 (02) ◽  
pp. 1750005 ◽  
Author(s):  
GAURAV KHANNA ◽  
RAJESH MISHRA ◽  
S. K. CHATURVEDI
Keyword(s):  
Interconnection Networks ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Cost Effective ◽  
Disjoint Paths ◽  
Multiple Processors ◽  
Memory Modules ◽  
Telephone Industry ◽  
Exchange Network ◽  
Shuffle Exchange Network

Advancement in technology has resulted in increased computing power with the use of multiple processors within a system. These multiple processors need to communicate with each other and with memory modules. Multistage Interconnection Networks (MINs) provide a communication medium in such multi-processor systems by interconnecting a number of processors and memory modules. Besides, MINs also provide a cost effective substitute to costly crossbars in parallel computers and switching systems in telephone industry. This paper introduces two new fault-tolerant MINs named as Shuffle Exchange Gamma Interconnection Networks (SEGIN-1 and SEGIN-2). SEGIN-1 and SEGIN-2 can be obtained by altering Shuffle Exchange Network with one extra stage (SEN+) and provide two disjoint paths similar to it. Performance of SEGIN-1 and SEGIN-2 has been evaluated in terms of alternative paths, disjoint paths, reliability and hardware cost, and is compared with some very famous MINs like Shuffle Exchange Network (SEN), Shuffle Exchange Network with one extra stage (SEN+), Shuffle Exchange Network with two extra stage (SEN+2), Extra Stage Cube (ESC) and Gamma Interconnection Network (GIN). Results suggest that SEGINs surpass all the compared networks; hence, the proposed designs seem to be suitable for implementing practical interconnection networks.

scholarly journals Cluster-Fault Tolerant Routing in a Torus

Sensors ◽  
2020 ◽  
Vol 20 (11) ◽  
pp. 3286 ◽  
Author(s):  
Antoine Bossard ◽  
Keiichi Kaneko
Keyword(s):  
Free Path ◽  
Time Complexity ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Routing Algorithm ◽  
Topological Properties ◽  
Huge Number ◽  
Worst Case ◽  
Faulty Node ◽  
Node Routing

The number of Internet-connected devices grows very rapidly, with even fears of running out of available IP addresses. It is clear that the number of sensors follows this trend, thus inducing large sensor networks. It is insightful to make the comparison with the huge number of processors of modern supercomputers. In such large networks, the problem of node faults necessarily arises, with faults often happening in clusters. The tolerance to faults, and especially cluster faults, is thus critical. Furthermore, thanks to its advantageous topological properties, the torus interconnection network has been adopted by the major supercomputer manufacturers of the recent years, thus proving its applicability. Acknowledging and embracing these two technological and industrial aspects, we propose in this paper a node-to-node routing algorithm in an n -dimensional k -ary torus that is tolerant to faults. Not only is this algorithm tolerant to faulty nodes, it also tolerates faulty node clusters. The described algorithm selects a fault-free path of length at most n ( 2 k + ⌊ k / 2 ⌋ − 2 ) with an O ( n 2 k 2 | F | ) worst-case time complexity with F the set of faulty nodes induced by the faulty clusters.

A COST-EFFECTIVE STREAMLINING OF THE DIOGENES DESIGN METHODOLOGY

1995 ◽  
Vol 05 (03) ◽  
pp. 513-524
Author(s):  
MARC PICQUENDAR ◽  
ARNOLD L. ROSENBERG ◽  
VITTORIO SCARANO
Keyword(s):  
Design Methodology ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
A Priori ◽  
Cost Effective ◽  
Fixed Number ◽  
Node Degree ◽  
Network Configuration ◽  
Optimal Network ◽  
Time Linear

The original DIOGENES design methodology produces fault-tolerant layouts of VLSI processor arrays by designing an array's interconnection network as a (possibly large) number of (re)configurable bundles of wires, each bundle being organized as either a stack or a queue. The benefits of DIOGENES often come only at high cost, in terms of both configuration hardware and algorithmic cost of configuration. In this paper, we improve the original methodology in a way that simultaneously: streamlines the design process; produces more cost-effective layouts; can be augmented to allow efficient dynamic reconfigurability. Our new version of DIOGENES replaces the wire-stacks and/or -queues of the original methodology by a single generalized deletion stack (GDS for short), independent of the topology of the array. The new methodology has three major benefits: 1. A GDS-network can be configured in time linear in the size of the graph being realized. (Optimal network configuration is superlinear for the queue-based version and NPcomplete for the stack-based version of the original methodology.) 2. A GDS-network can realize any linearization of any graph, subject only to the constraints of the implemented node-degree and cutwidth. (The original methodology demands a priori commitment to a fixed number of stacks or queues of fixed sizes, hence limits one to a restricted set of array topologies.) 3. A GDS-network usually requires dramatically less configuration hardware than a stack- or queue-based network would (albeit with larger switches). We end with suggested enhancements to this new, flexible, version of DIOGENES.

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