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Automated transistor sizing for FPGA architecture exploration
Proceedings of the 45th annual conference on Design automation - DAC '08
◽
10.1145/1391469.1391671
◽
2008
◽
Cited By ~ 11
Author(s):
Ian Kuon
◽
Jonathan Rose
Keyword(s):
Transistor Sizing
◽
Architecture Exploration
◽
Fpga Architecture
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References
A new coarse-grained FPGA architecture exploration environment
2008 International Conference on Field-Programmable Technology
◽
10.1109/fpt.2008.4762399
◽
2008
◽
Author(s):
Husain Parvez
◽
Zied Marrakchi
◽
Umer Farooq
◽
Habib Mehrez
Keyword(s):
Coarse Grained
◽
Architecture Exploration
◽
Fpga Architecture
◽
Exploration Environment
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Defect-Tolerant FPGA Architecture Exploration
2006 International Conference on Field Programmable Logic and Applications
◽
10.1109/fpl.2006.311253
◽
2006
◽
Cited By ~ 2
Author(s):
Pongstorn Maidee
◽
Kia Bazargan
Keyword(s):
Architecture Exploration
◽
Fpga Architecture
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MAPLE: A Machine Learning based Aging-Aware FPGA Architecture Exploration Framework
10.1109/fpl53798.2021.00070
◽
2021
◽
Author(s):
Behnam Ghavami
◽
Milad Ibrahimipour
◽
Zhenman Fang
◽
Lesley Shannon
Keyword(s):
Machine Learning
◽
Architecture Exploration
◽
Fpga Architecture
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Through Chip Interface Based Three-Dimensional FPGA Architecture Exploration
IEICE Transactions on Electronics
◽
10.1587/transele.e98.c.288
◽
2015
◽
Vol E98.C
(4)
◽
pp. 288-297
Author(s):
Li-Chung HSU
◽
Masato MOTOMURA
◽
Yasuhiro TAKE
◽
Tadahiro KURODA
Keyword(s):
Three Dimensional
◽
Architecture Exploration
◽
Fpga Architecture
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A Tile-based Interconnect Model for FPGA Architecture Exploration
Proceedings of the 2020 on Great Lakes Symposium on VLSI
◽
10.1145/3386263.3406927
◽
2020
◽
Author(s):
Chengyu Hu
◽
Qinghua Duan
◽
Peng Lu
◽
Wei Liu
◽
Jian Wang
◽
...
Keyword(s):
Architecture Exploration
◽
Fpga Architecture
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Visualization support for FPGA architecture exploration
2012 23rd IEEE International Symposium on Rapid System Prototyping (RSP)
◽
10.1109/rsp.2012.6380701
◽
2012
◽
Cited By ~ 2
Author(s):
Konstantin Nasartschuk
◽
Rainer Herpers
◽
Kenneth B. Kent
Keyword(s):
Architecture Exploration
◽
Fpga Architecture
Download Full-text
Three-Dimensional Tree-Based FPGA: Architecture Exploration Tools and Technologies
Lecture Notes in Electrical Engineering - Three-Dimensional Design Methodologies for Tree-based FPGA Architecture
◽
10.1007/978-3-319-19174-4_6
◽
2015
◽
pp. 117-146
Author(s):
Vinod Pangracious
◽
Zied Marrakchi
◽
Habib Mehrez
Keyword(s):
Three Dimensional
◽
Architecture Exploration
◽
Fpga Architecture
Download Full-text
Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design
2009 International Conference on Field-Programmable Technology
◽
10.1109/fpt.2009.5377647
◽
2009
◽
Cited By ~ 5
Author(s):
Alastair M. Smith
◽
George A. Constantinides
◽
Steven J. E. Wilton
◽
Peter Y. K. Cheung
Keyword(s):
Fpga Design
◽
Transistor Sizing
◽
Fpga Architecture
Download Full-text
A Fast Architecture Exploration Method for High Throughput IEEE 802.11e MAC Implementation Using SystemC
IEICE Transactions on Communications
◽
10.1587/transcom.e93.b.2833
◽
2010
◽
Vol E93-B
(10)
◽
pp. 2833-2836
Author(s):
Sung-Rok YOON
◽
Min Li HUANG
◽
Sangho SEO
◽
Hiroshi OCHI
◽
Sin-Chong PARK
Keyword(s):
High Throughput
◽
Ieee 802.11E
◽
Architecture Exploration
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Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences
◽
10.1587/transfun.e94.a.2499
◽
2011
◽
Vol E94-A
(12)
◽
pp. 2499-2509
◽
Cited By ~ 1
Author(s):
Seidai TAKEDA
◽
Kyundong KIM
◽
Hiroshi NAKAMURA
◽
Kimiyoshi USAMI
Keyword(s):
Current Model
◽
Input Vector
◽
Delay Estimation
◽
Transistor Sizing
◽
Linear Current
◽
Non Linear
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