Unidirectional Multi-Bit FPGA Architecture For Area Efficient Implementation of Datapath Circuits

Field Programmable Gate Arrays (FPGAs) are increasingly being used to implement large datapath-oriented application that are designed to process multiple-bit wide data. Studies have shown that the regularity of these multi-bit signals can be effectively exploited to reduce the implementation area of datapath circuits on FPGAs that employ the traditional bidirectional routing. Most of modern FPGAs, however, employ unidirectional routing tracks which are more area and delay efficient. No study has investigated the design of multi-bit routing resources that can effectively transport multiple-bit wide signals using unidirectional routing tracks. This paper presents such an investigation of architectures which employ multi-bit connections and unidirectional routing resources to exploit datapath regularity. It is experimentally shown that unidirectional multi-bit architectures are 8.6% more area efficient than the conventional architecture. Additionally, this paper determines the most are efficient proportion of multi-bit connections.

Unidirectional Multi-Bit FPGA Architecture For Area Efficient Implementation of Datapath Circuits

Field Programmable Gate Arrays (FPGAs) are increasingly being used to implement large datapath-oriented application that are designed to process multiple-bit wide data. Studies have shown that the regularity of these multi-bit signals can be effectively exploited to reduce the implementation area of datapath circuits on FPGAs that employ the traditional bidirectional routing. Most of modern FPGAs, however, employ unidirectional routing tracks which are more area and delay efficient. No study has investigated the design of multi-bit routing resources that can effectively transport multiple-bit wide signals using unidirectional routing tracks. This paper presents such an investigation of architectures which employ multi-bit connections and unidirectional routing resources to exploit datapath regularity. It is experimentally shown that unidirectional multi-bit architectures are 8.6% more area efficient than the conventional architecture. Additionally, this paper determines the most are efficient proportion of multi-bit connections.

The reduction of Crosstalk in VLSI due to parallel bus structure using Data Compression Bus Encoding technique implemented on Artix 7 FPGA Architecture

In this work, a bus encoding method is proposed that reduces the effect of crosstalk. The crosstalk usually occurs when the data is in parallel communicated. In planar structures, the crosstalk effect is large due to the usage of parallel communication and wide data patterns. In bus technique, the huge amount of wires is laid in equal over a significant time. One way to reduce crosstalk without changing the parallel communicating data lines is to reduce the wideband data patterns so as to reduce the power utilization. The proposed encoding method can minimize the crosstalk by reducing wide data patterns without degrading the performance. The architecture is implemented on Artix 7 FPGA at a 28nm technology node. The simulation is done using the HDL tool and the results are compared with the existing FPGA architecture. With the proposed method, the wire density and the power consumption are reduced by 57.4% and 50% respectively as compared with existing 45 nm technologies.