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The epsilon-approximation to discrete VT assignment for leakage power minimization
Proceedings of the 2009 International Conference on Computer-Aided Design - ICCAD '09
◽
10.1145/1687399.1687453
◽
2009
◽
Cited By ~ 2
Author(s):
Yujia Feng
◽
Shiyan Hu
Keyword(s):
Leakage Power
◽
Power Minimization
Download Full-text
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Cited By
References
Leakage Power Minimization
Low-Power VLSI Circuits and Systems
◽
10.1007/978-81-322-1937-8_9
◽
2014
◽
pp. 261-302
Author(s):
Ajit Pal
Keyword(s):
Leakage Power
◽
Power Minimization
Download Full-text
Dynamic and Leakage Power Minimization with Loop Voltage Scheduling and Assignment
2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing
◽
10.1109/euc.2008.90
◽
2008
◽
Author(s):
Meikang Qiu
◽
Jiande Wu
◽
Jingtong Hu
◽
Yi He
◽
Edwin H.-M. Sha
Keyword(s):
Leakage Power
◽
Power Minimization
Download Full-text
Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization
2007 44th ACM/IEEE Design Automation Conference
◽
10.1109/dac.2007.375129
◽
2007
◽
Author(s):
De-Shiuan Chiou
◽
Da-Cheng Juan
◽
Yu-Ting Chen
◽
Shih-Chieh Chang
Keyword(s):
Leakage Power
◽
Power Minimization
◽
Fine Grained
◽
Transistor Sizing
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Sleep Transistor Sizing for Leakage Power Minimization Considering Charge Balancing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
◽
10.1109/tvlsi.2008.2001247
◽
2009
◽
Vol 17
(9)
◽
pp. 1330-1334
◽
Cited By ~ 9
Author(s):
De-Shiuan Chiou
◽
Shih-Hsin Chen
◽
Shih-Chieh Chang
Keyword(s):
Leakage Power
◽
Power Minimization
◽
Transistor Sizing
◽
Charge Balancing
Download Full-text
A Genetic Algorithm Based Input State Assignment Technique for Leakage Power Minimization during Combinational Logic Synthesis
15th International Conference on Advanced Computing and Communications (ADCOM 2007)
◽
10.1109/adcom.2007.33
◽
2007
◽
Author(s):
Saurabh Chaudhury
◽
Ansuman Prusty
◽
Santanu Chattopadhyay
Keyword(s):
Genetic Algorithm
◽
Logic Synthesis
◽
Leakage Power
◽
Input State
◽
Combinational Logic
◽
Power Minimization
◽
State Assignment
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Neural network based optimization of CMOS transistor sizing for leakage power minimization
2012 International Conference on Innovations in Information Technology (IIT)
◽
10.1109/innovations.2012.6207724
◽
2012
◽
Author(s):
Omar Banimelhem
◽
Rami Bani Hani
Keyword(s):
Neural Network
◽
Leakage Power
◽
Power Minimization
◽
Transistor Sizing
◽
Cmos Transistor
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Activity profile driven simultaneous vt assignment and power switch sizing for leakage power minimization in nanometer CMOS designs
2010 17th IEEE International Conference on Electronics, Circuits and Systems
◽
10.1109/icecs.2010.5724563
◽
2010
◽
Cited By ~ 1
Author(s):
Ashoka Sathanur
◽
Jos Huisken
◽
Jan Stuyt
◽
Harmke de Groot
Keyword(s):
Leakage Power
◽
Power Minimization
◽
Activity Profile
◽
Nanometer Cmos
◽
Power Switch
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Leakage power minimization for the synthesis of parallel multiplier circuits
Proceedins of the 14th ACM Great Lakes symposium on VLSI - GLSVLSI '04
◽
10.1145/988952.988993
◽
2004
◽
Cited By ~ 1
Author(s):
Keoncheol Shin
◽
Taewhan Kim
Keyword(s):
Leakage Power
◽
Power Minimization
◽
Parallel Multiplier
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Post-layout leakage power minimization based on distributed sleep transistor insertion
Proceedings of the 2004 international symposium on Low power electronics and design - ISLPED '04
◽
10.1145/1013235.1013275
◽
2004
◽
Cited By ~ 9
Author(s):
Pietro Babighian
◽
Luca Benini
◽
Alberto Macii
◽
Enrico Macii
Keyword(s):
Leakage Power
◽
Power Minimization
Download Full-text
Statistical leakage power minimization using fast equi-slack shell based optimization
2007 44th ACM/IEEE Design Automation Conference
◽
10.1145/1278480.1278691
◽
2007
◽
Cited By ~ 1
Author(s):
Xiaoji Ye
◽
Yaping Zhan
◽
Peng Li
Keyword(s):
Leakage Power
◽
Power Minimization
Download Full-text
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