NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark

Compute-in-memory (CIM) is an attractive solution to process the extensive workloads of multiply-and-accumulate (MAC) operations in deep neural network (DNN) hardware accelerators. A simulator with options of various mainstream and emerging memory technologies, architectures, and networks can be a great convenience for fast early-stage design space exploration of CIM hardware accelerators. DNN+NeuroSim is an integrated benchmark framework supporting flexible and hierarchical CIM array design options from a device level, to a circuit level and up to an algorithm level. In this study, we validate and calibrate the prediction of NeuroSim against a 40-nm RRAM-based CIM macro post-layout simulations. First, the parameters of a memory device and CMOS transistor are extracted from the foundry’s process design kit (PDK) and employed in the NeuroSim settings; the peripheral modules and operating dataflow are also configured to be the same as the actual chip implementation. Next, the area, critical path, and energy consumption values from the SPICE simulations at the module level are compared with those from NeuroSim. Some adjustment factors are introduced to account for transistor sizing and wiring area in the layout, gate switching activity, post-layout performance drop, etc. We show that the prediction from NeuroSim is precise with chip-level error under 1% after the calibration. Finally, the system-level performance benchmark is conducted with various device technologies and compared with the results before the validation. The general conclusions stay the same after the validation, but the performance degrades slightly due to the post-layout calibration.

Synthesis of Classical and Non-Classical CMOS Transistor Fault Models Mapped to Gate-Level for Reconfigurable Hardware-Based Fault Injection

One of the main goals of fault injection techniques is to evaluate the fault tolerance of a design. To have greater confidence in the fault tolerance of a system, an accurate fault model is essential. While more accurate than gate level, transistor level fault models cannot be synthesized into FPGA chips. Thus, transistor level faults must be mapped to the gate level to obtain both accuracy and synthesizability. Re-synthesizing a large system for fault injection is not cost effective when the number of faults and system complexity are high. Therefore, the system must be divided into partitions to reduce the re-synthesis time as faults are injected only into a portion of the system. However, the module-based partial reconfiguration complexity rises with an increase in the total number of partitions in the system. An unbalanced partitioning methodology is introduced to reduce the total number of partitions in a system while the size of the partitions where faults are to be injected remains small enough to achieve an acceptable re-synthesis time.

Synthesis of Classical and Non-Classical CMOS Transistor Fault Models Mapped to Gate-Level for Reconfigurable Hardware-Based Fault Injection

One of the main goals of fault injection techniques is to evaluate the fault tolerance of a design. To have greater confidence in the fault tolerance of a system, an accurate fault model is essential. While more accurate than gate level, transistor level fault models cannot be synthesized into FPGA chips. Thus, transistor level faults must be mapped to the gate level to obtain both accuracy and synthesizability. Re-synthesizing a large system for fault injection is not cost effective when the number of faults and system complexity are high. Therefore, the system must be divided into partitions to reduce the re-synthesis time as faults are injected only into a portion of the system. However, the module-based partial reconfiguration complexity rises with an increase in the total number of partitions in the system. An unbalanced partitioning methodology is introduced to reduce the total number of partitions in a system while the size of the partitions where faults are to be injected remains small enough to achieve an acceptable re-synthesis time.

Study of the Absorption of Electromagnetic Radiation by 3D, Vacuum-Packaged, Nano-Machined CMOS Transistors for Uncooled IR Sensing

There is an ongoing effort to fabricate miniature, low-cost, and sensitive thermal sensors for domestic and industrial uses. This paper presents a miniature thermal sensor (dubbed TMOS) that is fabricated in advanced CMOS FABs, where the micromachined CMOS-SOI transistor, implemented with a 130-nm technology node, acts as a sensing element. This study puts emphasis on the study of electromagnetic absorption via the vacuum-packaged TMOS and how to optimize it. The regular CMOS transistor is transformed to a high-performance sensor by the micro- or nano-machining process that releases it from the silicon substrate by wafer-level processing and vacuum packaging. Since the TMOS is processed in a CMOS-SOI FAB and is comprised of multiple thin layers that follow strict FAB design rules, the absorbed electromagnetic radiation cannot be modeled accurately and a simulation tool is required. This paper presents modeling and simulations based on the LUMERICAL software package of the vacuum-packaged TMOS. A very high absorption coefficient may be achieved by understanding the physics, as well as the role of each layer.

Homodyne Spectroscopy with Broadband Terahertz Power Detector Based on 90-nm Silicon CMOS Transistor

Over the last two decades, photomixer-based continuous wave systems developed into versatile and practical tools for terahertz (THz) spectroscopy. The high responsivity to the THz field amplitude of photomixer-based systems is predetermined by the homodyne detection principle that allows the system to have high sensitivity. Here, we show that the advantages of homodyne detection can be exploited with broadband power detectors combined with two photomixer sources. For this, we employ a THz detector based on a complementary metal-oxide-semiconductor field-effect transistor and a broadband bow-tie antenna (TeraFET). At 500 GHz and an effective noise bandwidth of 1 Hz, the response from one photomixer-based THz source resulted in an about 43 dB signal-to-noise ratio (SNR). We demonstrate that by employing a homodyne detection system by overlaying the radiation from two photomixers, the SNR can reach up to 70 dB at the same frequency with an integration time 100 ms. The improvement in SNR and the spectroscopic evidence for water vapor lines demonstrated up to 2.2 THz allow us to conclude that these detectors can be successfully used in practical continuous wave THz spectrometry systems.

Implement Multichannel Fractional Sample Rate Convertor using Genetic Algorithm

In this paper reduce power of multichannel fractional sample rate convertor by minimized hamming distance between consecutive coefficients of filter using Genetic algorithm. The main component of multichannel fractional sample rate convertor is Cascaded multiple architecture finite impulse response filter (CMFIR filter). CMFIR is implemented by cascading of cascaded integrator-comb (CIC) & multiply accumulate architecture (MAC) FIR filter. Genetic algorithm minimizes the hamming distance between consecutive coefficients of CMFIR filter. By Minimizing the hamming distance of consecutive filter coefficient reduces the transaction from 0 to 1 or 1 to 0. These techniques reduce the switching activity of CMOS transistor which is directly reduces Dynamic power consumption by multichannel sample rate convertor, it also minimizes the total power consumption of multichannel fractional sample rate convertor. later than use genetic algorithm on 1 to 128 channel Down sample rate convertor total power reduced by 3.44% to 61.56%, dynamic power reduced by 9.09% to 56.25% .1 to 128 channel Up sample rate convertor total power reduced by 2.81% to 45.42%, dynamic power reduced by 4.76% to 56%, 1 to 128 channel fractional sample rate convertor total power reduced by 1.44% to 17.17%, dynamic power reduced by 6.25% to 19.92%.