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Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization
2007 44th ACM/IEEE Design Automation Conference
◽
10.1109/dac.2007.375129
◽
2007
◽
Author(s):
De-Shiuan Chiou
◽
Da-Cheng Juan
◽
Yu-Ting Chen
◽
Shih-Chieh Chang
Keyword(s):
Leakage Power
◽
Power Minimization
◽
Fine Grained
◽
Transistor Sizing
Download Full-text
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Cited By
References
Fine-grained sleep transistor sizing algorithm for leakage power minimization
2007 44th ACM/IEEE Design Automation Conference
◽
10.1145/1278480.1278502
◽
2007
◽
Cited By ~ 17
Author(s):
De-Shiuan Chiou
◽
Da-Cheng Juan
◽
Yu-Ting Chen
◽
Shih-Chieh Chang
Keyword(s):
Leakage Power
◽
Power Minimization
◽
Fine Grained
◽
Transistor Sizing
Download Full-text
Sleep Transistor Sizing for Leakage Power Minimization Considering Charge Balancing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
◽
10.1109/tvlsi.2008.2001247
◽
2009
◽
Vol 17
(9)
◽
pp. 1330-1334
◽
Cited By ~ 9
Author(s):
De-Shiuan Chiou
◽
Shih-Hsin Chen
◽
Shih-Chieh Chang
Keyword(s):
Leakage Power
◽
Power Minimization
◽
Transistor Sizing
◽
Charge Balancing
Download Full-text
Neural network based optimization of CMOS transistor sizing for leakage power minimization
2012 International Conference on Innovations in Information Technology (IIT)
◽
10.1109/innovations.2012.6207724
◽
2012
◽
Author(s):
Omar Banimelhem
◽
Rami Bani Hani
Keyword(s):
Neural Network
◽
Leakage Power
◽
Power Minimization
◽
Transistor Sizing
◽
Cmos Transistor
Download Full-text
Leakage Power Minimization of Nanoscale CMOS Circuits via Non-Critical Path Transistor Sizing
2006 13th IEEE International Conference on Electronics, Circuits and Systems
◽
10.1109/icecs.2006.379631
◽
2006
◽
Cited By ~ 1
Author(s):
Bo Fu
◽
Paul Ampadu
Keyword(s):
Critical Path
◽
Leakage Power
◽
Cmos Circuits
◽
Power Minimization
◽
Nanoscale Cmos
◽
Transistor Sizing
Download Full-text
Sleep Transistor Sizing for Leakage Power Minimization Considering Temporal Correlation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
◽
10.1109/tcad.2010.2046812
◽
2010
◽
Vol 29
(8)
◽
pp. 1285-1289
◽
Cited By ~ 3
Author(s):
De-Shiuan Chiou
◽
Yu-Ting Chen
◽
Da-Cheng Juan
◽
Shih-Chieh Chang
Keyword(s):
Temporal Correlation
◽
Leakage Power
◽
Power Minimization
◽
Transistor Sizing
Download Full-text
The epsilon-approximation to discrete VT assignment for leakage power minimization
Proceedings of the 2009 International Conference on Computer-Aided Design - ICCAD '09
◽
10.1145/1687399.1687453
◽
2009
◽
Cited By ~ 2
Author(s):
Yujia Feng
◽
Shiyan Hu
Keyword(s):
Leakage Power
◽
Power Minimization
Download Full-text
Leakage Power Minimization
Low-Power VLSI Circuits and Systems
◽
10.1007/978-81-322-1937-8_9
◽
2014
◽
pp. 261-302
Author(s):
Ajit Pal
Keyword(s):
Leakage Power
◽
Power Minimization
Download Full-text
Dynamic and Leakage Power Minimization with Loop Voltage Scheduling and Assignment
2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing
◽
10.1109/euc.2008.90
◽
2008
◽
Author(s):
Meikang Qiu
◽
Jiande Wu
◽
Jingtong Hu
◽
Yi He
◽
Edwin H.-M. Sha
Keyword(s):
Leakage Power
◽
Power Minimization
Download Full-text
Optimal Transistor Sizing of Full-Adder Block to Reduce Standby Leakage Power
Communications in Computer and Information Science - VLSI Design and Test
◽
10.1007/978-981-13-5950-7_8
◽
2019
◽
pp. 88-99
Author(s):
Prateek Gupta
◽
Shubham Kumar
◽
Zia Abbas
Keyword(s):
Full Adder
◽
Leakage Power
◽
Transistor Sizing
Download Full-text
Leakage Power Reduction for Deeply-Scaled FinFET Circuits Operating in Multiple Voltage Regimes Using Fine-Grained Gate-Length Biasing Technique
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015
◽
10.7873/date.2015.0520
◽
2015
◽
Cited By ~ 8
Author(s):
Ji Li
◽
Qing Xie
◽
Yanzhi Wang
◽
Shahin Nazarian
◽
Massoud Pedram
Keyword(s):
Power Reduction
◽
Leakage Power
◽
Gate Length
◽
Fine Grained
Download Full-text
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