Balancing the Leakage Currents in Nanometer CMOS Logic—A Challenging Goal

The imbalance of the currents leaked by CMOS standard cells when different logic values are applied to their inputs can be exploited as a side channel to recover the secrets of cryptographic implementations. Traditional side-channel countermeasures, primarily designed to thwart the dynamic leakage behavior, were shown to be much less powerful against this static threat. Thus, a special protection mechanism called Balanced Static Power Logic (BSPL) has been proposed very recently. Essentially, fundamental standard cells are re-designed to balance their drain-source leakage current independent of the given input. In this work, we analyze the BSPL concept in more detail and reveal several design issues that limit its effectiveness as a universal logic library. Although balancing drain-source currents remains a valid approach even in more advanced technology generations, we show that it is conceptually insufficient to achieve a fully data-independent leakage behavior in smaller geometries. Instead, we suggest an alternative approach, so-called improved BSPL (iBSPL). To evaluate the proposed method, we use information theoretic analysis. As an attack strategy, we have chosen Moments-Correlating DPA (MCDPA), since this analysis technique does not depend on a particular leakage model and allows a fair comparison. Through these evaluation methods, we show iBSPL demands fewer resources and delivers better balance in the ideal case as well as in the presence of process variations.

SC-DDPL as a Countermeasure against Static Power Side-Channel Attacks

With the continuous scaling of CMOS technology, which has now reached the 3 nm node at production level, static power begins to dominate the power consumption of nanometer CMOS integrated circuits. A novel class of security attacks to cryptographic circuits which exploit the correlation between the static power and the secret keys was introduced more than ten years ago, and, since then, several successful key recovery experiments have been reported. These results clearly demonstrate that attacks exploiting static power (AESP) represent a serious threat for cryptographic systems implemented in nanometer CMOS technologies. In this work, we analyze the effectiveness of the Standard Cell Delay-based Precharge Logic (SC-DDPL) style in counteracting static power side-channel attacks. Experimental results on an FPGA implementation of a compact PRESENT crypto-core show that the SC-DDPL implementation allows a great improvement of all the security metrics with respect to the standard CMOS implementation and other state-of-the-art countermeasures such as WDDL and MDPL.

ОСОБЕННОСТИ ПРОЕКТИРОВАНИЯ СБОЕУСТОЙЧИВЫХ СВЕРХБЫСТРОДЕЙСТВУЮЩИХ ЛОГИЧЕСКИХ ЦЕПЕЙ КМОП СБИС СНК

Проанализированы асимптотические параметры быстродействия нанометровых (суб-100 нм) КМОП-технологий объемного кремния (ОК) уровня 90-28 нм. Показано, что сбоеустойчивость логических цепей при воздействии отдельных ядерных частиц (ОЯЧ) зависит от частоты синхронизации СБИС и ухудшается при ее повышении. Даны рекомендации по проектированию сбоеустойчивых быстродействующих логических цепей в составе СБИС типа «система на кристалле» (СнК). The paper deals with asymptotic performance parameters of nanometer-CMOS technologies at a level of90-28 nm. It is shown that the single nuclear particle tolerance of logical circuits depends on the clock frequency of the VLSI circuit and worsens with its increase. Recommendations are given on the design of heavy-ion tolerant high-speed logic circuits in the system-on-chip (SoC) type VLSI.

A 1-nS 1-V Sub-1-µW Linear CMOS OTA with Rail-to-Rail Input for Hz-Band Sensory Interfaces

The paper presents an operational transconductance amplifier (OTA) with low transconductance (0.62–6.28 nS) and low power consumption (28–270 nW) for the low-frequency analog front-ends in biomedical sensor interfaces. The proposed OTA implements an innovative, highly linear voltage-to-current converter based on the channel-length-modulation effect, which can be rail-to-rail driven. At 1-V supply and 1-Vpp asymmetrical input driving, the linearity error in the current-voltage characteristics is 1.5%, while the total harmonic distortion (THD) of the output current is 0.8%. For a symmetrical 2-Vpp input drive, the linearity error is 0.3%, whereas THD reaches 0.2%. The linearity is robust for the mismatch and the process-voltage-and-temperature (PVT) variations. The temperature drift of transconductance is 10 pS/°C. The prototype circuit was fabricated in 180-nanometer CMOS technology.