A Reconfigurable Branch Predictor for Spatial Computing Architectures

Author(s):  
Yanan Lu ◽  
Leibo Liu ◽  
Jian Liu ◽  
Shouyi Yin ◽  
Shaojun Wei
Author(s):  
Johannes de Fine Licht ◽  
Andreas Kuster ◽  
Tiziano De Matteis ◽  
Tal Ben-Nun ◽  
Dominic Hofer ◽  
...  

2014 ◽  
Vol 72 (5) ◽  
pp. 1679-1693 ◽  
Author(s):  
Cong Thuan Do ◽  
Hong Jun Choi ◽  
Dong Oh Son ◽  
Jong Myon Kim ◽  
Cheol Hong Kim

2010 ◽  
Vol 53 (S1) ◽  
pp. 25-32 ◽  
Author(s):  
Lun Wu ◽  
MengLong Yan ◽  
Yong Gao ◽  
ZhenZhen Yang ◽  
Yong Zhao ◽  
...  

2012 ◽  
Vol 204-208 ◽  
pp. 4952-4957
Author(s):  
Ji Hua Ye ◽  
Qi Xie ◽  
Yao Hong Xiahou

Researched how the multi-pipeline processor accelerates the running of thread ,found that when the branch predictor facing the random branch instruction, the hit rate will become very low, so bring out a new method that using the free pipeline to accelerate the running of branch instruction. If the right prediction from branch predictor is less than 70% and there is a free pipeline, then using two pipelines to run the two sides of a branch instruction at the same time. In order to test the new method, the HLA (High Level architecture) architecture-based simulation system is established, the results show that the new method can really reduce the time when processing the random branch instructions.


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