Highly Concurrent Latency-tolerant Register Files for GPUs

ACM Transactions on Computer Systems ◽

10.1145/3419973 ◽

2021 ◽

Vol 37 (1--4) ◽

pp. 1-36

Author(s):

Mohammad Sadrosadati ◽

Amirhossein Mirhosseini ◽

Ali Hajiabadi ◽

Seyed Borna Ehsani ◽

Hajar Falahati ◽

...

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A compiler optimization to reduce soft errors in register files

Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems - LCTES '09 ◽

10.1145/1542452.1542459 ◽

2009 ◽

Author(s):

Jongeun Lee ◽

Aviral Shrivastava

Keyword(s):

Compiler Optimization ◽

Soft Errors ◽

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Code scheduling for VLIW/superscalar processors with limited register files

ACM SIGMICRO Newsletter ◽

10.1145/144965.145802 ◽

1992 ◽

Vol 23 (1-2) ◽

pp. 197-201

Author(s):

Tokuzo Kiyohara ◽

John C. Gyllenhaal

Keyword(s):

Superscalar Processors ◽

Register Files ◽

Code Scheduling

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Area and Timing Estimation in Register Files Using Neural Networks

Circuits and Systems ◽

10.4236/cs.2012.33037 ◽

2012 ◽

Vol 03 (03) ◽

pp. 269-277

Author(s):

Assim Sagahyroon ◽

Jamal Abdalla

Keyword(s):

Neural Networks ◽

Timing Estimation ◽

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Analysis of Soft Error Mitigation Techniques for Register Files in IBM Cu-08 90nm Technology

2006 49th IEEE International Midwest Symposium on Circuits and Systems ◽

10.1109/mwscas.2006.382112 ◽

2006 ◽

Author(s):

Riaz Naseer ◽

Rashed Zafar Bhatti ◽

Jeff Draper

Keyword(s):

Error Mitigation ◽

Register Files ◽

Mitigation Techniques ◽

Soft Error Mitigation

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Dynamic Capping of Physical Register Files in Simultaneous Multi-threading Processors for Performance

Communications in Computer and Information Science - Computer and Information Sciences ◽

10.1007/978-3-030-00840-6_5 ◽

2018 ◽

pp. 41-48

Author(s):

Hasancan Güngörer ◽

Gürhan Küçük

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Low power register files by eliminating redundant read

IEICE Electronics Express ◽

10.1587/elex.11.20140774 ◽

2014 ◽

Vol 11 (18) ◽

pp. 20140774-20140774

Author(s):

Leiou Wang ◽

Donghui Wang ◽

Huan Ying ◽

Chengpeng Hao

Keyword(s):

Low Power ◽

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Early Register Deallocation Mechanisms Using Checkpointed Register Files

IEEE Transactions on Computers ◽

10.1109/tc.2006.145 ◽

2006 ◽

Vol 55 (9) ◽

pp. 1153-1166 ◽

Author(s):

O. Ergin ◽

D. Balkan ◽

D. Ponomarev ◽

K. Ghose

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Exploiting Narrow Data-Width to Mask Soft Errors in Register Files

Lecture Notes in Computer Science - Computer Safety, Reliability, and Security ◽

10.1007/978-3-319-10506-2_9 ◽

2014 ◽

pp. 125-138 ◽

Author(s):

Jianjun Xu ◽

Qingping Tan ◽

Zeming Shao ◽

Hong Ning

Keyword(s):

Soft Errors ◽

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Drowsy Register Files for Reducing GPU Leakage Energy

2017 IEEE 23rd International Conference on Parallel and Distributed Systems (ICPADS) ◽

10.1109/icpads.2017.00087 ◽

2017 ◽

Author(s):

Xin Wang ◽

Wei Zhang

Keyword(s):

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Design of a motion compensation unit for H.264 decoder using 2-dimensional circular register files

2008 International SoC Design Conference ◽

10.1109/socdc.2008.4815696 ◽

2008 ◽

Author(s):

Chanho Lee ◽

Yonghoon Yu

Keyword(s):

Motion Compensation ◽

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