The impact of code density on instruction cache performance

Proceedings of the 16th annual international symposium on Computer architecture - ISCA '89 ◽

10.1145/74925.74954 ◽

1989 ◽

Author(s):

P. Steenkiste

Keyword(s):

Cache Performance ◽

Instruction Cache ◽

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The Impact Of Code Density On Instruction Cache Performance

The 16th Annual International Symposium on Computer Architecture ◽

10.1109/isca.1989.714560 ◽

2005 ◽

Author(s):

P. Steenkiste

Keyword(s):

Cache Performance ◽

Instruction Cache ◽

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The impact of code density on instruction cache performance

ACM SIGARCH Computer Architecture News ◽

10.1145/74926.74954 ◽

1989 ◽

Vol 17 (3) ◽

pp. 252-259

Author(s):

P. Steenkiste

Keyword(s):

Cache Performance ◽

Instruction Cache ◽

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On the Impact of OS and Linker Effects on Level-2 Cache Performance

14th IEEE International Symposium on Modeling, Analysis, and Simulation ◽

10.1109/mascots.2006.36 ◽

2006 ◽

Author(s):

H. Vandierendonck ◽

K. De Bosschere

Keyword(s):

Cache Performance ◽

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Achieving High Instruction Cache Performance With An Optimizing Compiler

The 16th Annual International Symposium on Computer Architecture ◽

10.1109/isca.1989.714559 ◽

2005 ◽

Author(s):

W.W. Hisu ◽

Pohua P. Chang

Keyword(s):

Cache Performance ◽

Instruction Cache ◽

Optimizing Compiler

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Improving Instruction Cache Performance by Dynamic Management of Cache-Image

KIISE Transactions on Computing Practices ◽

10.5626/ktcp.2017.23.9.564 ◽

2017 ◽

Vol 23 (9) ◽

pp. 564-571

Author(s):

Hyo-Joong Suh

Keyword(s):

Cache Performance ◽

Dynamic Management ◽

Instruction Cache ◽

Improving Instruction

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Achieving high instruction cache performance with an optimizing compiler

ACM SIGARCH Computer Architecture News ◽

10.1145/74926.74953 ◽

1989 ◽

Vol 17 (3) ◽

pp. 242-251 ◽

Author(s):

W. W. Hwu ◽

P. P. Chang

Keyword(s):

Cache Performance ◽

Instruction Cache ◽

Optimizing Compiler

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Evaluating the impact of dynamic binary translation systems on hardware cache performance

2008 IEEE International Symposium on Workload Characterization ◽

10.1109/iiswc.2008.4636098 ◽

2008 ◽

Author(s):

Arkaitz Ruiz-Alvarez ◽

Kim Hazelwood

Keyword(s):

Binary Translation ◽

Cache Performance ◽

Dynamic Binary Translation ◽

Translation Systems ◽

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Bounding pipeline and instruction cache performance

IEEE Transactions on Computers ◽

10.1109/12.743411 ◽

1999 ◽

Vol 48 (1) ◽

pp. 53-70 ◽

Author(s):

C.A. Healy ◽

R.D. Arnold ◽

F. Mueller ◽

D.B. Whalley ◽

M.G. Harmon

Keyword(s):

Cache Performance ◽

Instruction Cache

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Optimizing the instruction cache performance of the operating system

IEEE Transactions on Computers ◽

10.1109/12.737683 ◽

1998 ◽

Vol 47 (12) ◽

pp. 1363-1381 ◽

Author(s):

J. Torrellas ◽

Chun Xia ◽

R.L. Daigle

Keyword(s):

Operating System ◽

Cache Performance ◽

Instruction Cache

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The impact of extrinsic cache performance on predictability of real-time systems

Proceedings Second International Workshop on Real-Time Computing Systems and Applications ◽

10.1109/rtcsa.1995.528744 ◽

2002 ◽

Author(s):

J.V. Busquets-Mataix ◽

J.J. Serrano-Martin

Keyword(s):

Real Time ◽

Real Time Systems ◽

Cache Performance ◽

Time Systems ◽

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