This chapter presents a survey of parallel algorithms for computing the prefixes using circuit models. The circuits considered in this Chapter are constrained by the fixed fan-in (equal to two) but are allowed to have arbitrary or unbounded fan-out. Prefix circuits with fixed fan-in and fan-out are described in Chapter 7, and those with unbounded fan-in in Chapter 8. The characteristics of algorithms described in this Chapter are judged according to a number of measures including the size, depth, and fan-out. (Refer to Chapter 2 for definitions.) The layout of the serial circuit, S(N), is given in Figure 1. Clearly, the size, s(N), of this circuit is (N - 1), and the depth, d(N), is (N - 1). The sum of the size and depth for this circuit is. . . s(N) + d(N) = 2N – 2. . . . (1) Each node has a constant fan-out. In Chapter 6, it is shown that the sum of the size and depth of any prefix circuit is lower-bounded by 2N - 2. From this, it follows that the serial circuit is optimal. Thus, any circuit that computes all prefixes in less than serial time must have sizes larger than (N - 1). Perhaps an easy approach to the design of a parallel prefix circuit is to invoke the well known divide-conquer strategy. Let N = 2". According to this strategy, if DC(N) is a circuit that computes the prefixes of N elements, then DC (N) can be designed according to the principle illustrated in Figure 1.
POWER-SPEED TRADE-OFF IN PARALLEL PREFIX CIRCUITS
