scholarly journals SAT and CP - Parallelisation and Applications

2017 ◽  
Author(s):  
Thorsten Ehlers
Keyword(s):  
Parallel Implementation ◽  
Lower And Upper Bounds ◽  
Sat Solving ◽  
Learning Mechanisms ◽  
Sorting Networks ◽  
Parallel Solver ◽  
Sorting Algorithms ◽  
Programming Techniques ◽  
Oblivious Sorting

In this thesis, we consider the parallelisation and application of SAT and CP solvers. In the first chapter, we consider SAT, the decision problem of propositional logic. We discuss details of the implementations of SAT solvers, and show how to improve upon existing sequential solvers. Furthermore, we discuss the parallelisation of these solvers with a focus on the communication of intermediate results within a parallel solver. The second chapter is concerned with Contraint Programing (CP) with learning. Contrary to classical Constraint Programming techniques, this incorporates learning mechanisms as they are used in the field of SAT solving. We present results from parallelising CHUFFED, a learning CP solver. In the final chapter, we discuss Sorting Networks, which are data oblivious sorting algorithms. Their independence of the input data lends them to parallel implementation. We consider the question how many parallel sorting steps are needed to sort some inputs, and present both lower and upper bounds for several cases.

scholarly journals SAT and CP - Parallelisation and Applications

2017 ◽  
Author(s):  
Thorsten Ehlers
Keyword(s):  
Parallel Implementation ◽  
Lower And Upper Bounds ◽  
Sat Solving ◽  
Learning Mechanisms ◽  
Sorting Networks ◽  
Parallel Solver ◽  
Sorting Algorithms ◽  
Programming Techniques ◽  
Oblivious Sorting

In this thesis, we consider the parallelisation and application of SAT and CP solvers. In the first chapter, we consider SAT, the decision problem of propositional logic. We discuss details of the implementations of SAT solvers, and show how to improve upon existing sequential solvers. Furthermore, we discuss the parallelisation of these solvers with a focus on the communication of intermediate results within a parallel solver. The second chapter is concerned with Contraint Programing (CP) with learning. Contrary to classical Constraint Programming techniques, this incorporates learning mechanisms as they are used in the field of SAT solving. We present results from parallelising CHUFFED, a learning CP solver. In the final chapter, we discuss Sorting Networks, which are data oblivious sorting algorithms. Their independence of the input data lends them to parallel implementation. We consider the question how many parallel sorting steps are needed to sort some inputs, and present both lower and upper bounds for several cases.

A Sorting Network on Trees

2019 ◽  
Vol 29 (04) ◽  
pp. 1950015
Author(s):  
Avah Banerjee ◽  
Dana Richards
Keyword(s):  
Complete Graph ◽  
Maximum Degree ◽  
Graph Topology ◽  
Sorting Network ◽  
Sorting Networks ◽  
Underlying Graph ◽  
Sorting Algorithms ◽  
Oblivious Sorting

Sorting networks are a class of parallel oblivious sorting algorithms. Not only do they have interesting theoretical properties but they can be fabricated. A sorting network is a sequence of parallel compare-exchange operations using comparators which are grouped into stages. This underlying graph defines the topology of the network. The majority of results on sorting networks concern the unrestricted case where the underlying graph is the complete graph. Prior results are also known for paths, hypercubes, and meshes. In this paper we introduce a sorting network whose underlying topology is a tree and formalize the concept of sorting networks on a restricted graph topology by introducing a new parameter for graphs called its sorting number. The main result of the paper is a description of an [Formula: see text] depth sorting network on a tree with maximum degree [Formula: see text].

scholarly journals Parallel Computing for Sorting Algorithms

2014 ◽  
Vol 11 (2) ◽  
pp. 292-302
Author(s):  
Baghdad Science Journal
Keyword(s):  
Parallel Computing ◽  
Message Passing ◽  
Message Passing Interface ◽  
Parallel Implementation ◽  
Median Filter ◽  
Close Relation ◽  
C Programming Language ◽  
Sorting Algorithms ◽  
C Programming ◽  
Ordered Data

The expanding use of multi-processor supercomputers has made a significant impact on the speed and size of many problems. The adaptation of standard Message Passing Interface protocol (MPI) has enabled programmers to write portable and efficient codes across a wide variety of parallel architectures. Sorting is one of the most common operations performed by a computer. Because sorted data are easier to manipulate than randomly ordered data, many algorithms require sorted data. Sorting is of additional importance to parallel computing because of its close relation to the task of routing data among processes, which is an essential part of many parallel algorithms. In this paper, sequential sorting algorithms, the parallel implementation of many sorting methods in a variety of ways using MPICH.NT.1.2.3 library under C++ programming language and comparisons between the parallel and sequential implementations are presented. Then, these methods are used in the image processing field. It have been built a median filter based on these submitted algorithms. As the parallel platform is unavailable, the time is computed in terms of a number of computations steps and communications steps

A Practical Analysis of Oblivious Sorting Algorithms for Secure Multi-party Computation

2014 ◽  
pp. 59-74 ◽  
Author(s):  
Dan Bogdanov ◽  
Sven Laur ◽  
Riivo Talviste
Keyword(s):  
Sorting Algorithms ◽  
Practical Analysis ◽  
Oblivious Sorting

scholarly journals A Streaming High-Throughput Linear Sorter System with Contention Buffering

2011 ◽  
Vol 2011 ◽  
pp. 1-12 ◽  
Author(s):  
Jorge Ortiz ◽  
David Andrews
Keyword(s):  
High Throughput ◽  
Field Programmable Gate Array ◽  
Clock Cycle ◽  
Sorting Networks ◽  
Sorting Algorithms ◽  
Hardware Implementations ◽  
Field Programmable ◽  
Gate Array ◽  
Sorting Efficiency

Popular sorting algorithms do not translate well into hardware implementations. Instead, hardware-based solutions like sorting networks, systolic sorters, and linear sorters exploit parallelism to increase sorting efficiency. Linear sorters, built from identical nodes with simple control, have less area and latency than sorting networks, but they are limited in their throughput. We present a system composed of multiple linear sorters acting in parallel to increase overall throughput. Interleaving is used to increase bandwidth and allow sorting of multiple values per clock cycle, and the amount of interleaving and depth of the linear sorters can be adapted to suit specific applications. Contention for available linear sorters in the system is solved through the use of buffers that accumulate conflicting requests, dispatching them in bulk to reduce latency penalties. Implementation of this system into a field programmable gate array (FPGA) results in a speedup of 68 compared to a MicroBlaze processor running quicksort.

scholarly journals FPGA-Based Implementation of MMC Control Based on Sorting Networks

Energies ◽  
2018 ◽  
Vol 11 (9) ◽  
pp. 2394 ◽  
Author(s):  
Mattia Ricco ◽  
Laszlo Mathe ◽  
Eric Monmasson ◽  
Remus Teodorescu
Keyword(s):  
Execution Time ◽  
Sampling Period ◽  
Sorting Algorithm ◽  
Multilevel Converter ◽  
Voltage Balancing ◽  
Sorting Networks ◽  
Sorting Algorithms ◽  
And Performance ◽  
Proper Operation ◽  
Made In

In Modular Multilevel Converter (MMC) applications, the balancing of the capacitor voltages is one of the most important issues for achieving the proper behavior of the MMC. The Capacitor Voltage Balancing (CVB) control is usually based on classical sorting algorithms which consist of repetitive/recursive loops. This leads to an increase of the execution time when many Sub-Modules (SMs) are employed. When the execution time of the balancing is longer than the sampling period, the proper operation of the MMC cannot be ensured. Moreover, due to their inherent sequential operation, sorting algorithms are suitable for software implementation (microcontrollers or DSPs), but they are not appropriate for a hardware implementation. Instead, in this paper, Sorting Networks (SNs) are proposed due to their convenience for implementation in FPGA devices. The advantages and the main challenges of the Bitonic SN in MMC applications are discussed and different FPGA implementations are presented. Simulation results are provided in normal and faulty conditions. Moreover, a comparison with the widely used bubble sorting algorithm and max/min approach is made in terms of execution time and performance. Finally, hardware-in-the-loop results are shown to prove the effectiveness of the implemented SN.

Optimizing sorting algorithms by using sorting networks

2016 ◽  
Vol 29 (3) ◽  
pp. 559-579 ◽  
Author(s):  
Michael Codish ◽  
Luís Cruz-Filipe ◽  
Markus Nebel ◽  
Peter Schneider-Kamp
Keyword(s):  
Sorting Networks ◽  
Sorting Algorithms

scholarly journals Slowing down sorting networks to obtain faster sorting algorithms

1987 ◽  
Vol 34 (1) ◽  
pp. 200-208 ◽  
Author(s):  
Richard Cole
Keyword(s):  
Sorting Networks ◽  
Slowing Down ◽  
Sorting Algorithms

AI Programming Techniques: Good Medicine for Cognitive Modeling

1988 ◽  
Vol 33 (11) ◽  
pp. 973-974
Author(s):  
Charles R. Fletcher
Keyword(s):  
Cognitive Modeling ◽  
Good Medicine ◽  
Programming Techniques

Common Learning Mechanisms for Language and Music Grammar Acquisition

2014 ◽  
Author(s):  
Erica Knowles ◽  
Erin Ingvalson ◽  
Patrick Wong
Keyword(s):  
Learning Mechanisms ◽  
Grammar Acquisition ◽  
Language And Music ◽  
Common Learning
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