Lightweight cryptography is one of the efficient technologies that permit the confidentiality of communication through an insecure channel. Recently, several researchers have made a study on a lightweight block cipher in the field of cryptography. In this research paper we have concentrated on the design of lightweight block cipher with its performance evaluation and security analysis. We introduce RC7-RLGC algorithm, an FPGA implementation of Rivest's Cipher 7 (RC7) algorithm using reversible logic gates to encrypt the messages. The pseudorandom numbers are generated in Reversible Logic Gates Circuits (RLGCs) are used as key; this minimizes the resource utilization in encryption process. The proposed RC7-RLGC architecture has occupied less FPGA device utilization on LP-Virtex-6 device. It has occupied 13.04 % of LUTs, 10 % of flip-flops and 36.363 % of slices less than the existing RC7 algorithm.
FPGA Implementation of Parallel Adder Using Reversible Logic Gates
