An Experimental Evaluation of Resistive Defects and Different Testing Solutions in Low-Power Back-Biased SRAM Cells

This paper compares different types of resistive defects that may occur inside low-power SRAM cells, focusing on their impact on device operation. Notwithstanding the continuous evolution of SRAM device integration, manufacturing processes continue to be very sensitive to production faults, giving rise to defects that can be modeled as resistances, especially for devices designed to work in low-power modes. This work analyzes this type of resistive defect that may impair the device functionalities in subtle ways, depending on the defect characteristics and values that may not be directly or easily detectable by traditional test methods. We analyze each defect in terms of the possible effects inside the SRAM cell, its impact on power consumption, and provide guidelines for selecting the best test methods.

A Novel Design of High Performance and Robust Ultra-Low Power SRAM Cell Based on Memcapacitor

The present paper proposes a six-FinFET two-memcapacitor (6T2MC) non-volatile static random-access memory (NVSRAM). In this design, the two memcapacitors are used as non-volatile memory elements. The proposed cell is flexible against data loss when turned off and offers significant improvement in read and write operations compared to previous NVSRAMs. The performance of the new NVSRAM design is evaluated in terms of read and write operation at particular nanometric feature sizes. Moreover, the proposed 6T2MC cell is compared with 8T2R, 8T1R, 7T1R, and 7T2R cells. The results show that 6T2MC has a 5.50% lower write delay and 98.35% lower read delay compared to 7T2R and 7T1R cells, respectively. The 6T2MC cell exhibits 38.86% lower power consumption and 23.80% lower leakage power than 7T2R and 7T1R cells. The proposed cell is significantly improved in terms of HSNM, RSNM, and WSNM compared to 8T2R, 8T1R, 7T2R, and 7T1R cells, respectively. Important cell parameters, such as power consumption, data read/write delay, and SNM, are significantly improved. The superior characteristics of FinFET over MOSFET and the combination of this technology with memcapacitors lead to significant improvement in the proposed design.

Design and Analysis of Soft Error Rate in FET/CNTFET Based Radiation Hardened SRAM Cell

Aerospace equipages encounter potential radiation footprints through which soft errors occur in the memories onboard. Hence, robustness against radiation with reliability in memory cells is a crucial factor in aerospace electronic systems. This work proposes a novel Carbon nanotube field-effect transistor (CNTFET) in designing a robust memory cell to overcome these soft errors. Further, a petite driver circuit to test the SRAM cells which serve the purpose of precharge and sense amplifier, and has a reduction in threefold of transistor count is recommended. Additionally, analysis of robustness against radiation in varying memory cells is carried out using standard GPDK 90 nm, GPDK 45 nm, and 14 nm CNTFET. The reliability of memory cells depends on the critical charge of a device, and it is tested by striking an equivalent current charge of the cosmic ray’s linear energy transfer (LET) level. Also, the robustness of the memory cell is tested against the variation in process, voltage and temperature. Though CNTFET surges with high power consumption, it exhibits better noise margin and depleted access time. GPDK 45 nm has an average of 40% increase in SNM and 93% reduction of power compared to the 14 nm CNTFET with 96% of surge in write access time. Thus, the conventional MOSFET’s 45 nm node outperforms all the configurations in terms of static noise margin, power, and read delay which swaps with increased write access time.

A loadless 4T SRAM powered by gate leakage current with a high tolerance for fluctuations in device parameters

A novel loadless four-transistor static random access memory cell is proposed that consists of two N-type driver MOSFETs and two P-type access ones whose gate leakage currents from word-line are used for holding data in the cell. It is shown that the proposed cell has a higher tolerance for manufacturing device fluctuations compared with the conventional loadless 4T SRAM. Furthermore, it is free from bit-line disturb in contrast to the conventional cell. It is confirmed by simulation in 32nm technology node that the read static noise margin of the proposed cell reaches 138.7% of the six-transistor SRAM cell and that the hold static noise margin can be acceptable when the gate insulator thickness of the P-type access MOSFETs is made thinner than the N-type driver MOSFETs. The retention current for the proposed cell decreases to 66.7% of the 6TSRAM and the data rate in read increases to 125%.

Performance Analysis of 6T SRAM and ONOFIC Cells

Background: As the Technology node scales down to deep sub-micron regime, the design of static random-access memory (SRAM) cell becomes a critical issue because of increased leakage current components. These leakage current components prevent to design a low power processor as large of the processor power is consumed by the memory part. Objective: In this paper, a SRAM cell is designed based on ON/OFF logic (ONOFIC) approach. Static noise margin (SNM) of the cell for the different states are calculated and evaluated by using butterfly as well as noise (N) curves with the help of Cadence tools at 45 nm technology node. Methods: ONOFIC approach helps to reduce the leakage current components which makes a low power memory cell. A performance comparison is made between the conventional six-transistor (6T) SRAM cell and memory cell using ONOFIC approach. Results: Low value of power delay product (PDP) is the outcome of ONOFIC approach as compared to conventional cell. ONOFIC approach decreases PDP by 99.99% in case of hold state. Conclusions: ONOFIC approach improves the different performance metrics for the different states of the SRAM cell.

A 9T FinFET SRAM cell for ultra-low power application in the subthreshold regime

Due to the scaling of the CMOS, the limitations of these devices raised the need for alternative nano-devices. Various devices are proposed like FinFET, TFET, CNTFET. Among these, the FinFET emerges as one of the promising devices which can replace the CMOS due to its low leakage in the nanometer regime. The electronics devices are nowadays more compact and efficient in terms of battery consumption. The CMOS SRAMs have been replaced by the FinFET SRAMs due to the scaling limitations of the CMOS. Two FinFET SRAM cells have been which power efficient are and having high stability. Performance comparison of these cells has been done to analyze the leakage power and the static noise margins. The simulation of the cells is done at 20 nm FinFET technology. It has been analyzed that the write margin of improved 9T SRAM cell achieves an improvement of 1.49x. The read margin is also showing a drastic improvement over the existing cells which has been compared in the paper. The hold margin was found to be better in the case of the proposed SRAM cell at 0.4 V. The gate length has been varied to find the effect on read margin with gate length.