Lightweight VLSI Architectures for Image Encryption Applications

Lightweight cryptography offers significant security service in constrained environments such as wireless sensor networks and Internet of Things. The focus of this article is to construct lightweight SPN block cipher architectures with substitution box based on finite fields. The paper also details the FPGA implementation of the lightweight symmetric block cipher algorithm of SPN type with combinational S-box. Restructuring of traditional look-up-table Substitution Box (S-Box) sub-structure with a combinational logic S-box is attempted. Elementary architectures namely the basic round architecture and reduced datawidth architecture incorporating look-up-table and combinational S-Box substructure are compared in terms of area and throughput. Proposed restructure mechanism occupies less FPGA resources with no comprise in the latency and also demonstrates performance efficiency and low power consumption in Xilinx FPGAs. Robustness of the proposed method against various statistical attacks has been analyzed through comparison with other existing encryption mechanisms.

Designing an Efficient and Highly Dynamic Substitution-Box Generator for Block Ciphers Based on Finite Elliptic Curves

Developing a substitution-box (S-box) generator that can efficiently generate a highly dynamic S-box with good cryptographic properties is a hot topic in the field of cryptography. Recently, elliptic curve (EC)-based S-box generators have shown promising results. However, these generators use large ECs to generate highly dynamic S-boxes and thus may not be suitable for lightweight cryptography, where the computational power is limited. The aim of this paper is to develop and implement such an S-box generator that can be used in lightweight cryptography and perform better in terms of computation time and security resistance than recently designed S-box generators. To achieve this goal, we use ordered ECs of small size and binary sequences to generate certain sequences of integers which are then used to generate S-boxes. We performed several standard analyses to test the efficiency of the proposed generator. On an average, the proposed generator can generate an S-box in 0.003 seconds, and from 20,000 S-boxes generated by the proposed generator, 93 % S-boxes have at least the nonlinearity 96. The linear approximation probability of 1000 S-boxes that have the best nonlinearity is in the range [0.117, 0.172] and more than 99% S-boxes have algebraic complexity at least 251. All these S-boxes have the differential approximation probability value in the interval [0.039, 0.063]. Computational results and comparisons suggest that our newly developed generator takes less running time and has high security against modern attacks as compared to several existing well-known generators, and hence, our generator is suitable for lightweight cryptography. Furthermore, the usage of binary sequences in our generator allows generating plaintext-dependent S-boxes which is crucial to resist chosen-plaintext attacks.

Transparency order versus confusion coefficient: a case study of NIST lightweight cryptography S-Boxes

Side-channel resistance is nowadays widely accepted as a crucial factor in deciding the security assurance level of cryptographic implementations. In most cases, non-linear components (e.g. S-Boxes) of cryptographic algorithms will be chosen as primary targets of side-channel attacks (SCAs). In order to measure side-channel resistance of S-Boxes, three theoretical metrics are proposed and they are reVisited transparency order (VTO), confusion coefficients variance (CCV), and minimum confusion coefficient (MCC), respectively. However, the practical effectiveness of these metrics remains still unclear. Taking the 4-bit and 8-bit S-Boxes used in NIST Lightweight Cryptography candidates as concrete examples, this paper takes a comprehensive study of the applicability of these metrics. First of all, we empirically investigate the relations among three metrics for targeted S-boxes, and find that CCV is almost linearly correlated with VTO, while MCC is inconsistent with the other two. Furthermore, in order to verify which metric is more effective in which scenarios, we perform simulated and practical experiments on nine 4-bit S-Boxes under the non-profiled attacks and profiled attacks, respectively. The experiments show that for quantifying side-channel resistance of S-Boxes under non-profiled attacks, VTO and CCV are more reliable while MCC fails. We also obtain an interesting observation that none of these three metrics is suitable for measuring the resistance of S-Boxes against profiled SCAs. Finally, we try to verify whether these metrics can be applied to compare the resistance of S-Boxes with different sizes. Unfortunately, all of them are invalid in this scenario.

Constructing an optimum 4×4 S-Box with quasigroup

The efficiency of cryptographic algorithms is a problem that is often encountered. One solution of this problem is the use of lightweight cryptography. S-Box is one of the basic non-linear components in a cryptographic algorithm. Among all, 4 × 4 S-Box quasigroup is one kind of S-Box which can be used in lightweight cryptography, that formed by applying quasigroup transformation. The research described in this paper is the construction of the 4 × 4 S-Box using e-transformation of quasigroup as well as to know which leader pattern produces the highest number of optimum S-Box and mostly has higher Robustness value. The construction resulted in 6912 4 × 4 S-Boxes quasigroup by applying for each six leader patterns in four e-transformation rounds of 432 nonlinear quasigroups. The results of 4 × 4 S-Box quasigroup is calculated based on criteria of optimum 4 × 4 S-Box that has higher Robustness value. From all results of the 4 × 4 S-Box quasigroup, it is known that the leader pattern producing S-Box which meet the criteria and all S-Boxes have highest Robustness value are l 1 l 2 l 1 l 2 and l 1 l 2 l 1 l 2. The number of S-Box which meet the criteria is 18,75% of the total 5376 different 4 × 4 S-Boxes quasigroup and the highest Robustness value is 0,75.

Lightweight Cryptography for the Encryption of Data Communication of IoT Devices

We are at the beginning of the age of the Internet of things. Soon, we will be surrounded by smart homes, cities, and infrastructure. To achieve this vision, millions of devices will have to be able to communicate with each other. The demands for communication channels will increase significantly. An increasing amount of data will be transmitted with a requirement of minimal delay. The capacities of transmission systems can be quickly depleted. Building new communication channels is very time consuming but also financially demanding. To maximize existing infrastructure, we should pay attention today to the issue of transmitted data. One of the ways is to focus attention on reducing the volume of transmitted data. In this paper, we present a method of reducing the volume of data transmission between a server and an IoT device, focusing on the bandwidth, transmission security, and system resources of the IoT device. The required reduction is achieved by data compression and replacing the SSL/TLS cryptographic protocol with lightweight cryptography based on the Vernam cipher principle. The original SSL/TLS protocol is still used for device management needs only.

Efficient hardware implementation for lightweight mCrypton algorithm using FPGA

<p>The lightweight cryptography is used for low available resources devices such as radio frequency identification (RFID) tags, internet of things (IoTs) and wireless sensor networks. In such case, the lightweight cryptographic algorithms should consider power consumption, design area, speed, and throughput. This paper presents a new architecture of mCrypton lightweight cryptographic algorithm which considers the above-mentioned conditions. Resource-shared structure is used to reduce the area of the new architecture. The proposed architecture is implemented using ISE Xilinx V14,5 and Spartan 3 FPGA platform. The simulation results introduced that the proposed design area is 375 of slices, up to 302 MHz operating frequency, a throughput of 646 Mbps, efficiency of 1.7 Mbps/slice and 0.089 Watt power consumption. Thus, the proposed architecture outperforms similar architectures in terms of area, speed, efficiency and throughput.</p>