scholarly journals EMPLOYING MULTI-CORE PROCESSOR ARCHITECTURES TO ACCELERATE JAVA CRYPTOGRAPHY EXTENSIONS

2011 ◽  
Keyword(s):  
Processor Architectures ◽  
Multi Core Processor

scholarly journals Efficient local locking for massively multithreaded in-memory hash-based operators

2021 ◽  
Author(s):  
Bashar Romanous ◽  
Skyler Windh ◽  
Ildar Absalyamov ◽  
Prerna Budhkar ◽  
Robert Halstead ◽  
...  
Keyword(s):  
Relational Databases ◽  
Aggregation Operators ◽  
Main Memory ◽  
Paradigm Shifts ◽  
Multithreaded Processors ◽  
Cache Hierarchies ◽  
Processor Architectures ◽  
Spatial Locality ◽  
Content Addressable Memories ◽  
Multi Core Processor

AbstractThe join and group-by aggregation are two memory intensive operators that are affecting the performance of relational databases. Hashing is a common approach used to implement both operators. Recent paradigm shifts in multi-core processor architectures have reinvigorated research into how the join and group-by aggregation operators can leverage these advances. However, the poor spatial locality of the hashing approach has hindered performance on multi-core processor architectures which rely on using large cache hierarchies for latency mitigation. Multithreaded architectures can better cope with poor spatial locality by masking memory latency with many outstanding requests. Nevertheless, the number of parallel threads, even in the most advanced multithreaded processors, such as UltraSPARC, is not enough to fully cover the main memory access latency. In this paper, we explore the hardware re-configurability of FPGAs to enable deeper execution pipelines that maintain hundreds (instead of tens) of outstanding memory requests across four FPGAs-drastically increasing concurrency and throughput. We present two end-to-end in-memory accelerators for the join and group-by aggregation operators using FPGAs. Both accelerators use massive multithreading to mask long memory delays of traversing linked-list data structures, while concurrently managing hundreds of thread states across four FPGAs locally. We explore how content addressable memories can be intermixed within our multithreaded designs to act as a synchronizing cache, which enforces locks and merges jobs together before they are written to memory. Throughput results for our hash-join operator accelerator show a speedup between 2$$\times $$ × and 3.4$$\times $$ × over the best multi-core approaches with comparable memory bandwidths on uniform and skewed datasets. The accelerator for the hash-based group-by aggregation operator demonstrates that leveraging CAMs achieves average speedup of 3.3$$\times $$ × with a best case of 9.4$$\times $$ × in terms of throughput over CPU implementations across five types of data distributions.

Parallel techniques for physically based simulation on multi-core processor architectures

2008 ◽  
Vol 32 (1) ◽  
pp. 25-40 ◽  
Author(s):  
Bernhard Thomaszewski ◽  
Simon Pabst ◽  
Wolfgang Blochinger
Keyword(s):  
Physically Based Simulation ◽  
Processor Architectures ◽  
Physically Based ◽  
Parallel Techniques ◽  
Multi Core Processor

Proposal and Evaluation of Mutual Exclusion Method using Lock-free Algorism for Embedded Systems using Multi-core Processor

2019 ◽  
Vol 139 (7) ◽  
pp. 802-811
Author(s):  
Kenta Fujimoto ◽  
Shingo Oidate ◽  
Yuhei Yabuta ◽  
Atsuyuki Takahashi ◽  
Takuya Yamasaki ◽  
...  
Keyword(s):  
Embedded Systems ◽  
Mutual Exclusion ◽  
Exclusion Method ◽  
Multi Core Processor
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