Efficient VLSI Architecture for Memetic Vector Quantizer Design

A LEARNING PARALLEL ANALOG-TO-DIGITAL VECTOR QUANTIZER

Journal of Circuits System and Computers ◽

10.1142/s0218126698000389 ◽

1998 ◽

Vol 08 (05n06) ◽

pp. 605-614 ◽

Cited By ~ 2

Author(s):

JEREMY LUBKIN ◽

GERT CAUWENBERGHS

Keyword(s):

Vlsi Architecture ◽

Mos Transistors ◽

Resonance Theory ◽

Self Organizing Maps ◽

Adaptive Resonance ◽

Analog To Digital ◽

Vector Quantizer ◽

Digital Format ◽

Analog Memory ◽

On Chip

A mixed-mode VLSI architecture for learning vector quantization (LVQ), with on-chip adaptation and dynamic storage of the analog templates, converts analog vectorial data in parallel to digital format. The architecture is digitally configurable, and extends to commonly used algorithms for codebook adaptation besides k-means clustering such as Fuzzy Adaptive Resonance Theory (ART) and Kohonen self-organizing maps. The analog memory and adaptive element of the LVQ cell comprise 6 MOS transistors and one capacitor, and provide for robust self-refresh of the dynamic analog storage. Total cell size including distance and adaptive computations is 80×70 lambda in scalable MOSIS technology. Experimental results from a fabricated 16×16 cell prototype in 2μm CMOS are included.

VLSI Architecture for Fast Memetic Vector Quantizer Design on Reconfigurable Hardware

Algorithms and Architectures for Parallel Processing - Lecture Notes in Computer Science ◽

10.1007/978-3-642-03095-6_49 ◽

2009 ◽

pp. 513-524

Author(s):

Sheng-Kai Weng ◽

Chien-Min Ou ◽

Wen-Jyi Hwang

Keyword(s):

Vlsi Architecture ◽

Reconfigurable Hardware ◽

Vector Quantizer

A VLSI architecture for a real-time code book generator and encoder of a vector quantizer

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/92.311645 ◽

1994 ◽

Vol 2 (3) ◽

pp. 360-364 ◽

Cited By ~ 21

Author(s):

K. Tsang ◽

B.W.Y. Wei

Keyword(s):

Real Time ◽

Vlsi Architecture ◽

Time Code ◽

Vector Quantizer ◽

Code Book

A VLSI architecture for real time code book generator and encoder of a vector quantizer

Proceedings of 3rd IEEE International Conference on Image Processing ◽

10.1109/icip.1996.561072 ◽

2002 ◽

Author(s):

A. Brahmbhatt

Keyword(s):

Real Time ◽

Vlsi Architecture ◽

Time Code ◽

Vector Quantizer ◽

Code Book

A Low-Power VLSI Architecture for HEVC De-Quantization and Inverse Transform

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e99.a.2375 ◽

2016 ◽

Vol E99.A (12) ◽

pp. 2375-2387

Author(s):

Heming SUN ◽

Dajiang ZHOU ◽

Shuping ZHANG ◽

Shinji KIMURA

Keyword(s):

Low Power ◽

Vlsi Architecture ◽

Inverse Transform

A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard

IEICE Electronics Express ◽

10.1587/elex.10.20130210 ◽

2013 ◽

Vol 10 (9) ◽

pp. 20130210-20130210 ◽

Cited By ~ 2

Author(s):

Hong Liang ◽

He Weifeng ◽

Zhu Hui ◽

Mao Zhigang

Keyword(s):

Block Size ◽

Vlsi Architecture

Novel Bit-Sliced Near-Memory Computing Based VLSI Architecture for Fast Sobel Edge Detection in IoT Edge Devices

2020 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) ◽

10.1109/ises50453.2020.00071 ◽

2020 ◽

Author(s):

Rajeev Joshi ◽

Md Adnan Zaman ◽

Srinivas Katkoori

Keyword(s):

Edge Detection ◽

Vlsi Architecture ◽

Sobel Edge Detection

A Novel VLSI Architecture for Barrel Distortion Correction

2020 International Computer Symposium (ICS) ◽

10.1109/ics51289.2020.00050 ◽

2020 ◽

Author(s):

Chi-Ting Ni ◽

Chen-An Chang ◽

Jia-Wei Liao ◽

Pei-Yin Chen

Keyword(s):

Vlsi Architecture ◽

Distortion Correction ◽

Barrel Distortion

Ultralow-Latency VLSI Architecture Based on a Linear Approximation Method for Computing Nth Roots of Floating-Point Numbers

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2020.3038417 ◽

2020 ◽

pp. 1-13

Author(s):

Fei Lyu ◽

Xiaoqi Xu ◽

Yu Wang ◽

Yuanyong Luo ◽

Yuxuan Wang ◽

...

Keyword(s):

Linear Approximation ◽

Approximation Method ◽

Vlsi Architecture ◽

Floating Point ◽

Linear Approximation Method ◽

Floating Point Numbers

An Efficient NLMS-based VLSI Architecture for Robust FECG Extraction and FHR Processing

2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) ◽

10.1109/icecs49266.2020.9294943 ◽

2020 ◽

Author(s):

Patricia U. L. da Costa ◽

Guilherme Paim ◽

Leandro Rocha ◽

Eduardo da Costa ◽

Sergio Almeida ◽

...

Keyword(s):

Vlsi Architecture