analog to digital
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Author(s):  
Vo Trung Dung Huynh ◽  
Linh Mai ◽  
Hung Ngoc Do ◽  
Minh Ngoc Truong Nguyen ◽  
Trung Kien Pham

<span>High-speed Terahertz communication systems has recently employed orthogonal frequency division multiplexing approach as it provides high spectral efficiency and avoids inter-symbol interference caused by dispersive channels. Such high-speed systems require extremely high-sampling <br /> time-interleaved analog-to-digital converters at the receiver. However, timing mismatch of time-interleaved analog-to-digital converters significantly causes system performance degradation. In this paper, to avoid such performance degradation induced by timing mismatch, we theoretically determine maximum tolerable mismatch levels for orthogonal frequency division multiplexing communication systems. To obtain these levels, we first propose an analytical method to derive the bit error rate formula for quadrature and pulse amplitude modulations in Rayleigh fading channels, assuming binary reflected gray code (BRGC) mapping. Further, from the derived bit error rate (BER) expressions, we reveal a threshold of timing mismatch level for which error floors produced by the mismatch will be smaller than a given BER. Simulation results demonstrate that if we preserve mismatch level smaller than 25% of this obtained threshold, the BER performance degradation is smaller than 0.5 dB as compared to the case without timing mismatch.</span>


Micromachines ◽  
2022 ◽  
Vol 13 (1) ◽  
pp. 114
Author(s):  
Dongdong Chen ◽  
Xinhui Cui ◽  
Qidong Zhang ◽  
Di Li ◽  
Wenyang Cheng ◽  
...  

As traditional ultrasonic imaging systems (UIS) are expensive, bulky, and power-consuming, miniaturized and portable UIS have been developed and widely utilized in the biomedical field. The performance of integrated circuits (ICs) in portable UIS obviously affects the effectiveness and quality of ultrasonic imaging. In the ICs for UIS, the analog-to-digital converter (ADC) is used to complete the conversion of the analog echo signal received by the analog front end into digital for further processing by a digital signal processing (DSP) or microcontroller unit (MCU). The accuracy and speed of the ADC determine the precision and efficiency of UIS. Therefore, it is necessary to systematically review and summarize the characteristics of different types of ADCs for UIS, which can provide valuable guidance to design and fabricate high-performance ADC for miniaturized high resolution UIS. In this paper, the architecture and performance of ADC for UIS, including successive approximation register (SAR) ADC, sigma-delta (Σ-∆) ADC, pipelined ADC, and hybrid ADC, have been systematically introduced. In addition, comparisons and discussions of different types of ADCs are presented. Finally, this paper is summarized, and presents the challenges and prospects of ADC ICs for miniaturized high resolution UIS.


Author(s):  
Hiroki Sonoda ◽  
Takuji Miki ◽  
Makoto Nagata

Abstract Internet-of-things (IoT) devices are compact and low power. A voltage-controlled oscillator (VCO) based analog-to-digital converter (ADC) benefits from scaled CMOS transistors in representing analog signals in the time domain and therefore meets those demands. However, we find the potential drawback of VCO-based ADCs for the electromagnetic susceptibility (EMS) to radio-frequency (RF) disturbances that are essentially present in IoT environment. It is exhibited that the single and even differential designs of VCO-based ADC suffer from the EMS by RF disturbance, which behaves differently from the known common-mode noise rejection. A 28-nm CMOS 10-bit VCO-ADC prototype exhibit the sensitivity against RF signals in the widely used 2.4 GHz frequency band.


2022 ◽  
Vol 17 ◽  
pp. 1-15
Author(s):  
G. Vasudeva ◽  
B. V. Uma

Successive Approximation Register (SAR) Analog to Digital Converter (ADC) architecture comprises of sub modules such as comparator, Digital to Analog Converter and SAR logic. Each of these modules imposes challenges as the signal makes transition from analog to digital and vice-versa. Design strategies for optimum design of circuits considering 22nm FinFET technology meeting area, timing, power requirements and ADC metrics is presented in this work. Operational Transconductance Amplifier (OTA) based comparator, 12-bit two stage segmented resistive string DAC architecture and low power SAR logic is designed and integrated to form the ADC architecture with maximum sampling rate of 1 GS/s. Circuit schematic is captured in Cadence environment with optimum geometrical parameters and performance metrics of the proposed ADC is evaluated in MATLAB environment. Differential Non Linearity and Integral Non Linearity metrics for the 12-bit ADC is limited to +1.15/-1 LSB and +1.22/-0.69 LSB respectively. ENOB of 10.1663 with SNR of 62.9613 dB is achieved for the designed ADC measured for conversion of input signal of 100 MHz with 20dB noise. ADC with sampling frequency upto 1 GSps is designed in this work with low power dissipation less than 10 mW.


Author(s):  
Takuji Miki ◽  
Makoto Nagata

Abstract Cryptographic ICs on edge devices for internet-of-things (IoT) applications are exposed to an adversary and threatened by malicious side channel analysis. On-chip analog monitoring by sensor circuits embedded inside the chips is one of the possible countermeasures against such attacks. An on-chip monitor circuit consisting of a successive approximation register (SAR) analog-to-digital converter (ADC) and an input buffer acquires a wideband signal, which enables to detects an irregular noise due to an active fault injection and a passive side channel leakage analysis. In this paper, several countermeasures against security attacks utilizing wideband on-chip monitors are reviewed. Each technique is implemented on a prototype chip, and the measurement results prove they can effectively detect and diagnose the security attacks.


2022 ◽  
pp. 185-196
Author(s):  
Ryan Shook

In efforts to strengthen its digitization program, the University Libraries of University of Guam have assembled members from its Robert F. Kennedy Memorial Library and Micronesian Area Research Center to identify standards and frameworks to facilitate sustainable, long-term access and preservation of its indigenous and historic collections. Following the 2019 Pacific Islands Association of Libraries Annual Conference hosted at the University of Guam RFK Library and the unveiling of the Para Hulo' Strategic Plan, a greater institutional emphasis has been placed on the need for digitally accessible archives and remote access. University Libraries investigates the need to balance utilitarian functions of traditional librarianship with the democratic ideals inherent in the profession, as expressed through revisiting a range of literature to articulate the connections between digital librarianship, traditional librarianship, and analog to digital conversion.


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