A Formal Approach for RT-DVS Algorithms Evaluation Based on Statistical Model Checking

Energy saving is a crucial concern in embedded real time systems. Many RT-DVS algorithms have been proposed to save energy while preserving deadline guarantees. This paper presents a novel approach to evaluate RT-DVS algorithms using statistical model checking. A scalable framework is proposed for RT-DVS algorithms evaluation, in which the relevant components are modeled as stochastic timed automata, and the evaluation metrics including utilization bound, energy efficiency, battery awareness, and temperature awareness are expressed as statistical queries. Evaluation of these metrics is performed by verifying the corresponding queries using UPPAAL-SMC and analyzing the statistical information provided by the tool. We demonstrate the applicability of our framework via a case study of five classical RT-DVS algorithms.

Utilization Bound Scheduling Analysis for Nonpreemptive Uniprocessor Architecture Using UML-RT

The key for adopting the utilization-based schedulability test is to derive the utilization bound. Given the computation times, this paper proposes two utilization bound algorithms to derive interrelease times for nonpreemptive periodic tasks, using a new priority scheme, “Rate Monotonic Algorithm-Shortest Job First.” The obtained task set possesses the advantage of Rate Monotonic Algorithm and Shortest Job First priority scheme. Further, the task set is tested for schedulability, by first deriving a general schedulability condition from “problem window” analysis and, a necessary and sufficient schedulability condition for a task to be scheduled, at any release time are also derived. As a technical contribution, success ratio and effective processor utilization are analyzed for our proposed utilization bound algorithms on a uniprocessor architecture modeled using UML-RT.