Thermal Resistance of Cascade Heat Pipe as CPU Cooling System to Maintain Safe Temperature for Computer

Computer will overheat quickly if used in a state of full load continuously. One component on a computer that generates heat is the central processing unit (CPU) which is a key component on a computer where program instructions are processed. One of the right solutions to cool the CPU is the use of heat pipes as cooling system, using several size container, loaded with a special liquid liquid to deliver the heat from the evaporator zone to the other end called condenser zone, but because the heat pipe condenser output temperature is still high therefore a cascade heat pipe was created to lower the output temperature. In this study there are four CPU cooling systems used namely single condenser cascade heat pipe and a double condenser cascade heat pipe, while others two cooling systems as a comparison namely non-cascade heat pipe and non-cascade heat pipe with fan. This study aims to find out the cooling performance of cascade heat pipe as CPU cooling system in a small form factor desktop PC by testing variations in workload, the workload given is idle load (12W) where the processor only runs the operating system without the software load so the processor utilization is only 1% -10%. Next is the medium load (30W) that uses 2 threads with processor utilization of 50% -90%. The last workload is full load (35W) with the number of threads used being 4 with processor utilization of 90% -100%. This research found that the thermal resistance of the cascade heat pipe tended to be higher than that of the non-cascade heat pipe, however the increase that occurred was not too large compared to the resulting performance of 60.2°C in the processor and 40.4°C in the heat sink for the cascade double condenser, the operating temperature of the CPU does not increase significantly as the thermal resistance increases on the cascade heat pipe.

Multiple Processor Scheduling with Optimum Execution Time and Processor Utilization Based on the SOSA

The multiple processor scheduling problem characterizes that different processor comprises of an arrangement of jobs or tasks designate proficient utilizing a limited number of processors. Herein development a multi-objective algorithm utilizing Symbiotic Organisms Search algorithm (SOSA) for scheduling an arrangement of reliant on tasks on obtainable resources in a multiple processor environment which minimizes the execution time and maximize the processor utilization. SOSA is a nature-inspired meta-heuristic algorithm utilized to compare with other meta-heuristic algorithms such as Water cycle algorithm (WCA), Genetic algorithm based Bacteria foraging optimization (GBF), Bacteria Foraging Optimization (BFO) and Genetic Algorithm (GA). SOSA reproduces the advantageous association methodologies received by life forms to survive and engender in the biological-community (ecosystem). Based on experimental results, we find the execution time as well as processor utilization using SOSA technique and then compare with the other mentioned algorithms. Acquired outcomes affirm the incredible execution of the SOSA in solving the multiple processor scheduling problems.

Utilization Bound Scheduling Analysis for Nonpreemptive Uniprocessor Architecture Using UML-RT

The key for adopting the utilization-based schedulability test is to derive the utilization bound. Given the computation times, this paper proposes two utilization bound algorithms to derive interrelease times for nonpreemptive periodic tasks, using a new priority scheme, “Rate Monotonic Algorithm-Shortest Job First.” The obtained task set possesses the advantage of Rate Monotonic Algorithm and Shortest Job First priority scheme. Further, the task set is tested for schedulability, by first deriving a general schedulability condition from “problem window” analysis and, a necessary and sufficient schedulability condition for a task to be scheduled, at any release time are also derived. As a technical contribution, success ratio and effective processor utilization are analyzed for our proposed utilization bound algorithms on a uniprocessor architecture modeled using UML-RT.