Cascade Products of Stochastic Automata

Stochastic Moore automata have in opposition to stochastic Mealy automata the same capabilities as general stochastic automata, but have the advantage that they are easier to access than their pure stochastic counterparts. Cascade decomposition of automata leads to a loop-free partitioning and in this way contributes to the analysis of automata. This paper shows that stochastic Moore automata can be decomposed into cascade products of stochastic Moore automata under mild conditions

Synthesis of a combined automaton with ASIC

Introduction. The model of a finite state machine is widely used for describing behavior of different sequential blocks, such as control units. It is possible that control units possess output signals having both types of Mealy and Moore automata. A model of the combined automaton can be used to synthesize such devices. When the automaton circuit is implemented, it is necessary to optimize its characteristics such as hardware amount. The methods of this task solution depend significantly on logic elements used to implement circuits. In this article, we propose a method of reducing hardware in the circuit of combined automaton implemented with ASIC. In this case, the circuit is implemented using customized matrix circuits. The proposed method allows reducing the chip area occupied by the circuit of the automaton. The method is based on the expansion of the matrix that generates circuit product terms of the systems of input memory functions and output functions of the combined automaton. The additional part of the matrix generates terms for output functions of Moore automaton. It allows reduction of the chip area as compared to the area of the two-level circuit of the combined automaton. The purpose of the article is to show that the division of circuit matrices allows reducing the resulting matrix area. The hardware amount is estimated for both trivial automaton structure and for the proposed approach. They are determined in conventional units of area. Results. The method is proposed based on the expansion of the matrix of terms. Using an example, it is shown how to execute the steps of the proposed method. To increase the method efficiency, it is proposed to use a special state assignment that minimizes the number of terms in the systems of Boolean functions of outputs with Moore type. The conducted investigations show that the proposed method allows for reducing the resulting ASIC area from 10% to 26%. The gain increases with the growth of the automaton complexity. Conclusions. A comparison of the proposed method with some known synthesis methods shows that the expansion of the matrix of terms for systems of input memory functions and output functions allows reducing the chip area occupied by the circuit of the combined automaton. Keywords: combined automaton, ASIC, synthesis, state encoding, matrix circuit.

A coalgebraic view on decorated traces

In the concurrency theory, various semantic equivalences on transition systems are based on traces decorated with some additional observations, generally referred to as decorated traces. Using the generalized powerset construction, recently introduced by a subset of the authors (Silva et al.2010 FSTTCS. LIPIcs8 272–283), we give a coalgebraic presentation of decorated trace semantics. The latter include ready, failure, (complete) trace, possible futures, ready trace and failure trace semantics for labelled transition systems, and ready, (maximal) failure and (maximal) trace semantics for generative probabilistic systems. This yields a uniform notion of minimal representatives for the various decorated trace equivalences, in terms of final Moore automata. As a consequence, proofs of decorated trace equivalence can be given by coinduction, using different types of (Moore-) bisimulation (up-to context).

Completeness Conditions of Systems of Moore Automata

This paper describes sufficient completeness conditions for the class of Moore automata, compositions with feedback on this class and the behavior realization. It is shown how to realize a delay by automata from the set satisfying sufficient conditions for completeness. The ideas of these constructions demonstrate how from a set of automata with long cycles of transients can be realized a delay with short cycle of transient. It is shown that there are large finite complete sets of automata, for which any proper subsets are not complete.