Wafer-Level Chip-Scale Packaging
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10

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Published By Springer New York

9781493915552, 9781493915569

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Thermal Management, Design, and Analysis for WLCSP

Wafer-Level Chip-Scale Packaging ◽

10.1007/978-1-4939-1556-9_7 ◽

2014 ◽

pp. 147-172

Author(s):

Shichun Qu ◽

Yong Liu

Keyword(s):

Thermal Management

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Electrical and Multiple Physics Simulation for Analog and Power WLCSP

Wafer-Level Chip-Scale Packaging ◽

10.1007/978-1-4939-1556-9_8 ◽

2014 ◽

pp. 173-225

Author(s):

Shichun Qu ◽

Yong Liu

Keyword(s):

Physics Simulation

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Fan-Out Wafer-Level Chip-Scale Package

Wafer-Level Chip-Scale Packaging ◽

10.1007/978-1-4939-1556-9_3 ◽

2014 ◽

pp. 39-62

Author(s):

Shichun Qu ◽

Yong Liu

Keyword(s):

Wafer Level ◽

Chip Scale Package

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Fan-In Wafer-Level Chip-Scale Package

Wafer-Level Chip-Scale Packaging ◽

10.1007/978-1-4939-1556-9_2 ◽

2014 ◽

pp. 15-38

Author(s):

Shichun Qu ◽

Yong Liu

Keyword(s):

Wafer Level ◽

Chip Scale Package

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WLCSP Assembly

Wafer-Level Chip-Scale Packaging ◽

10.1007/978-1-4939-1556-9_9 ◽

2014 ◽

pp. 227-255

Author(s):

Shichun Qu ◽

Yong Liu

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Wafer-Level Packaging TSV/Stack Die for Integration of Analog and Power Solution

Wafer-Level Chip-Scale Packaging ◽

10.1007/978-1-4939-1556-9_6 ◽

2014 ◽

pp. 119-146

Author(s):

Shichun Qu ◽

Yong Liu

Keyword(s):

Wafer Level ◽

Wafer Level Packaging

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Stackable Wafer-Level Analog Chip-Scale Package

Wafer-Level Chip-Scale Packaging ◽

10.1007/978-1-4939-1556-9_4 ◽

2014 ◽

pp. 63-90

Author(s):

Shichun Qu ◽

Yong Liu

Keyword(s):

Wafer Level ◽

Chip Scale Package

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WLCSP Typical Reliability and Test

Wafer-Level Chip-Scale Packaging ◽

10.1007/978-1-4939-1556-9_10 ◽

2014 ◽

pp. 257-317

Author(s):

Shichun Qu ◽

Yong Liu

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Wafer-Level Discrete Power Mosfet Package Design

Wafer-Level Chip-Scale Packaging ◽

10.1007/978-1-4939-1556-9_5 ◽

2014 ◽

pp. 91-117

Author(s):

Shichun Qu ◽

Yong Liu

Keyword(s):

Wafer Level ◽

Power Mosfet ◽

Package Design

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Demand and Challenges for Wafer-Level Chip-Scale Analog and Power Packaging

Wafer-Level Chip-Scale Packaging ◽

10.1007/978-1-4939-1556-9_1 ◽

2014 ◽

pp. 1-14

Author(s):

Shichun Qu ◽

Yong Liu

Keyword(s):

Wafer Level

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