Reliability of one-shot device with generalized gamma lifetime under cyclic accelerated life-test

One-shot devices are products or equipments that can be used only once. A nature characteristic of one-shot devices is that they get destroyed immediately after their use, and therefore their actual lifetimes are never observable. The only information observed is the condition whether they worked or not at the time they are used. These days the quality of products are significantly improved, so that the information obtained under a normal test during a short time is quite limited. A typical test to induce more failures is the accelerated life-test, which is developed by increasing the stress levels under test. In this paper, we will investigate the reliability of one-shot devices with generalized gamma fatigue life under accelerated life-tests with various cyclic temperature fluctuations by assuming a Norris-Landzberg model. Generalized gamma involves many common lifetime distributions, such as gamma, Weibull, lognormal, and positive stable distributions, as special cases. Norris-Landzberg model takes not only temperature change, highest testing temperature, but also the cycling frequency into account when modeling the number of cycles-to-failure, resulting a generalized model with the well-known Coffin-Manson model and Coffin-Manson-Arrhenius model as special cases. Associated inferences are developed. The performance of the proposed model and inferential methods will be evaluated with simulation study and model discrimination. Finally, the chip-scale package solder joints data is analyzed to illustrate the considered model and inferential methods developed in this paper.

Design for Reliability of Automotive Chip Scale Packages by Calibrated Virtual Prototyping

The thermomechanical reliability of the package and interconnections of assembled flip chip ball grid arrays (FC-BGA) is investigated in comparison to a reference chip scale package (CSP). Comparison is made using finite element (FE-) simulation. A combined measuring-simulation technique is applied to calibrate the finite element simulations on a reference object. Adjustment is made based on the in-plane deformation field evaluated by both simulation and optical measurement. For the latter an optical sensor for in-plane deformation and strain field analysis is used based on grey scale correlation method. A methodology is presented and to extrapolate the knowledge gained to alternative package types of different but similar design in order to evaluate their suitability for the desired application before the physical fabrication (virtual prototyping).

Thermal Cycling Test and Simulation of Six-Side Molded Panel-Level Chip-Scale Packages (PLCSPs)

In this study, the reliability of the solder joints of a six-side molded panel-level chip-scale package (PLCSP) is investigated. Emphasis is placed on the thermal cycling test (−55°C Δ 125°C, 50-min cycle) of the six-side molded PLCSP on a printed circuit board. For comparison purpose, the one without six-side molded (ordinary) PLCSP is also subjected to the same test. The thermal cycling test results are plotted into a Weibull distribution, and the true Weibull slope and true characteristic life at 90% confidence are presented. The solder joint mean life ratio of these two cases and its confidence level are also determined. Furthermore, their solder joint failure location and failure mode are provided. Finally, a nonlinear, time- and temperature-dependent 3-D finite element simulation is performed for these two cases and correlated with the thermal cycling test results.

Impact of Conformal Coating Induced Stress on Wafer Level Chip Scale Package Thermal Cycling Performance

Conformal coating is commonly used for harsh environment to protect electronics from moisture and chemical contaminants. But the stresses imparted by the conformal coating can cause degradation to the package thermal cycle performance. Full coverage of the component with conformal coating material can prevent potential corrosion induced degradation but imply a local compression stress during thermal cycling, resulting a different thermal cycling performance compared to non-coated components. In this study, 8x8mm2 wafer level chip scale packages (WLCSP) were subjected to 5% NaCl aqueous spray test with and without full conformal coating, then thermal cycled from -40ºC to +125ºC. Weibull reliability statistics indicated that fully conformal coated components experience characteristic life cycle number reduction from 404 cycles to 307 cycles, a 24% lifetime reduction, comparing to no conformal coated, no salt spray test applied components. The correlation between crack propagation and localized recrystallization were compared in a series of cross section analyses using polarized imaging and electro-backscattered diffraction, which revealed that the conformal coating induced a z-axis tension and compression strain during thermal cycling, resulting in an accelerated degradation at the solder interconnect. Linear Laser profilometer measurements showed that fully conformal coated samples experienced a higher z-axis height displacement change relative to non-conformal coated samples when exposed to 125 °C with 10 minutes dwell. To prevent this z-axis strain a reworkable edgebond adhesive was applied with full conformal coating configuration, which demonstrate an increase of characteristic lifecycle number to 2783 cycles, suggesting that the mitigation of the z-axis strain can vastly enhance the thermal cycling performance.

Six-Side Molded Panel-Level Chip-Scale Package with Multiple Diced Wafers

In this study, the design, materials, process, assembly, and reliability of a six-side molded panel-level chip-scale package (PLCSP) are presented. Emphasis is placed on the fabrication of the redistribution layers (RDLs) of the PLCSP on a large temporary panel with multiple device wafers. Because all the printed circuited board (PCB) panels are in rectangular shape, some of the device wafers are diced into two or more pieces so the panel is fully utilized. Thus, it is very high throughput. Because all the processes/equipment are PCB processes/equipment (not semiconductor process/equipment), it is a very low-cost process. After the fabrication of RDLs, the wafers from the PCB panel were debonded. It is followed by solder ball mounting and fabricating the six-side molded PLCSP from the original device wafers with RDLs. The drop test and the results including failure analysis of the PLCSP are presented. Thermal cycling of the six-side molded PLCSP PCB assembly is performed by a nonlinear temperature- and time-dependent finite-element simulation.