Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing
Latest Publications

TOTAL DOCUMENTS

(FIVE YEARS 0)

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(FIVE YEARS 0)

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0818671025

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

An efficient test method for embedded multi-port RAM with BIST circuitry

Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.1995.518083 ◽

2002 ◽

Cited By ~ 18

Author(s):

T. Matsumura

Keyword(s):

Test Method ◽

Efficient Test

Logic-enhanced memories for data-intensive processing

Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.1995.518087 ◽

2002 ◽

Cited By ~ 4

Author(s):

S. Van Singel ◽

N. Soparkar

Keyword(s):

Data Intensive ◽

Intensive Processing

Yield and cost estimation for a CAM based parallel processor

Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.1995.518091 ◽

2002 ◽

Cited By ~ 1

Author(s):

W.B. Noghani ◽

I.P. Jalowiecki

Keyword(s):

Cost Estimation ◽

Parallel Processor

Automatic computation of test length for pseudo-random memory tests

Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.1995.518082 ◽

2002 ◽

Cited By ~ 1

Author(s):

A.J. van de Goor

Keyword(s):

Test Length ◽

Automatic Computation ◽

Memory Tests

Detection of faults in ECL storage elements

Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.1995.518081 ◽

2002 ◽

Author(s):

S.M. Menon ◽

A. Nymoen

A 2 cycle 1 Mbit 4 way set associative 4 way interleave multi-processor L2 directory with array access/cycle 2.5 nsec

Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.1995.518085 ◽

2002 ◽

Author(s):

G.M. Lattimore ◽

M. Kumar ◽

J.M. Poplawski

A bipartite, differential I/sub DDQ/ testable static RAM design

Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.1995.518079 ◽

2002 ◽

Author(s):

W.K. Al-Assadi ◽

A.P. Jayasumana ◽

Y.K. Malaiya

Keyword(s):

Static Ram

A new serial sensing approach for multistorage non-volatile memories

Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.1995.518077 ◽

2002 ◽

Cited By ~ 7

Author(s):

C. Calligaro ◽

V. Daniele ◽

R. Gastaldi ◽

A. Manstretta ◽

G. Torelli

A modeling and circuit reduction methodology for circuit simulation of DRAM circuits

Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.1995.518076 ◽

2002 ◽

Cited By ~ 1

Author(s):

W.H. Kao ◽

X.C. Gao ◽

R. Hamazaki ◽

H. Kikuchi

Keyword(s):

Circuit Simulation

Optimization of memory organization and hierarchy for decreased size and power in video and image processing systems

Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.1995.518086 ◽

2002 ◽

Cited By ~ 19

Author(s):

L. Nachtergaele ◽

F. Catthoor ◽

F. Balasa ◽

F. Franssen ◽

E. De Greef ◽

...

Keyword(s):

Image Processing ◽

Memory Organization

Records of the 1995 IEEE International Workshop on Memory Technology, Design and TestingLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

An efficient test method for embedded multi-port RAM with BIST circuitry

Logic-enhanced memories for data-intensive processing

Yield and cost estimation for a CAM based parallel processor

Automatic computation of test length for pseudo-random memory tests

Detection of faults in ECL storage elements

A 2 cycle 1 Mbit 4 way set associative 4 way interleave multi-processor L2 directory with array access/cycle 2.5 nsec

A bipartite, differential I/sub DDQ/ testable static RAM design

A new serial sensing approach for multistorage non-volatile memories

A modeling and circuit reduction methodology for circuit simulation of DRAM circuits

Optimization of memory organization and hierarchy for decreased size and power in video and image processing systems

Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing
Latest Publications