A Native SPICE Implementation of Memristor Models for Simulation of Neuromorphic Analog Signal Processing Circuits

Since the memristor emerged as a programmable analog storage device, it has stimulated research on the design of analog/mixed-signal circuits with the memristor as the enabler of in-memory computation. Due to the difficulty in evaluating the circuit-level nonidealities of both memristors and CMOS devices, SPICE-accuracy simulation tools are necessary for perfecting the art of neuromorphic analog/mixed-signal circuit design. This article is dedicated to a native SPICE implementation of the memristor device models published in the open literature and develops case studies of applying such a circuit simulation with MOSFET models to study how device-level imperfections can make adversarial effects on the analog circuits that implement neuromorphic analog signal processing. Methods on memristor stamping in the framework of modified nodal analysis formulation are presented, and implementation results are reported. Furthermore, functional simulations on neuromorphic signal processing circuits including memristors and CMOS devices are carried out to validate the effectiveness of the native SPICE implementation of memristor models from the perspectives of simulation accuracy, efficiency, and convergence for large-scale simulation tasks.

A Novel Synthetization Approach for Multi Coupled Line Section Impedance Transformers in Wideband Applications

In this paper, a novel synthetization approach is proposed for filter-integrated wideband impedance transformers (ITs). The original topology consists of N cascaded coupled line sections (CLSs) with 2N characteristic impedance parameters. By analyzing these characteristic impedances, a Chebyshev response can be derived to consume N + 2 design conditions. To optimize the left N − 2 variable parameters, CLSs were newly substituted by transmission lines (TLs) to consume the remaining variable parameters and simplify the circuit topology. Therefore, there are totally 2N − N − 2 substituting possibilities. To verify the proposed approach, 25 cases are listed under the condition of N = 5, and 7 selected cases are compared and discussed in detail. Finally, a 75–50 Ω IT with 100% fractional bandwidth and 20 dB bandpass return loss (RL) is designed and fabricated. The measured results meet the circuit simulation and the EM simulation accurately.

Measurement and data-assisted simulation of bit error rate in RQL circuits

A circuit-simulation-based method is used to determine the thermally-induced bit error rate of superconducting Single Flux Quantum logic circuits. Simulations are used to evaluate the multidimensional Gaussian integral across noise current sources attached to the active devices. The method is data-assisted and has predictive power. Measurement determines the value of a single parameter, effective noise bandwidth, for each error mechanism. The errors in the distributed networks of comparator-free Reciprocal Quantum Logic nucleate across multiple Josephson junctions, so the effective critical current is about three times that of the individual devices. The effective noise bandwidth is only 6%–23% of the junction plasma frequency at a modest clock rate of 3.4 GHz, which is 1% of the plasma frequency. This analysis shows the ways measured bit error rate comes out so much lower than simplistic estimates based on isolated devices.

Theoretical Study of a Two-Degree-of-Freedom Piezoelectric Energy Harvester under Concurrent Aeroelastic and Base Excitation

This paper presents a study of a two-degree-of-freedom (2DOF) piezoelectric energy harvester (PEH) under concurrent aeroelastic and base excitation. The governing equations of the theoretical model under the combined excitation are developed and solved analytically using the harmonic balance method. Based on the electro-mechanical analogies, an equivalent circuit model is established. The energy harvesting performance of the 2DOF PEH under different wind speeds but the same base excitation is investigated. Voltage amplitudes of various response components with different frequencies are predicted by the analytical method and verified by the circuit simulation. The root-mean-square (RMS) voltage is used to measure the actual performance of the 2DOF PEH. Around the resonance state, the 2DOF PEH has been found to produce a larger voltage output than the conventional SDOF PEH. Moreover, several interesting phenomena, such as the quasi-periodic oscillation and the peak-to-valley transition, have been observed in the circuit simulation and explained by the analytical solution. The developed methodology in this paper can be easily adapted to analyze other similar types of multiple-degree-of-freedom (MDOF) PEHs under concurrent aeroelastic and base excitation.

In situ monitoring of the electrical property of carbon nanotube thin film in floating catalyst chemical vapor deposition

In floating catalyst chemical vapor deposition (FCCVD), when a carbon nanotube (CNT) network film is produced by filter collection, the film thickness is adjusted by controlling the collection time. However, even with consistent synthesis parameters, the synthesis condition in FCCVD changes constantly depending on the carbon and catalyst adhesion to the inner wall of the reaction tube. Thus, the rate of synthesis changes, making it difficult to obtain the target film thickness repeatedly and stably. We propose a method of monitoring CNT film thickness and percolation threshold by the in situ measurement of the electrical impedance during the deposition. The time evolution of the measured impedance is reproducible by an equivalent electrical circuit simulation.

An IDA-PBC Design with Integral Action for Output Voltage Regulation in an Interleaved Boost Converter for DC Microgrid Applications

This paper describes the output voltage regulation control for an interleaved connected to a direct current (DC) microgrid considering bidirectional current flows. The proposed controller is based on an interconnection and damping passivity-based control (IDA-PBC) approach with integral action that regulates the output voltage profile at its assigned reference. This approach designs a control law via nonlinear feedback that ensures asymptotic stability in a closed-loop in the sense of Lyapunov. Moreover, the IDA-PBC design adds an integral gain to eliminate the possible tracking errors in steady-state conditions. Numerical simulations in the Piecewise Linear Electrical Circuit Simulation (PLECS) package for MATLAB/Simulink demonstrate that the effectiveness of the proposed controller is assessed and compared with a conventional proportional-integral controller under different scenarios considering strong variations in the current injected/absorbed by the DC microgrid.

Monolithic 3D Inverter with Interface Charge: Parameter Extraction and Circuit Simulation

We have simulated a monolithic three-dimensional inverter (M3DINV) structure by considering the interfacial trap charges generated thermally during the monolithic three-dimensional integration process. We extracted the SPICE model parameters from M3DINV structures with two types of inter-layer dielectric thickness TILD (=10, 100 nm) using the extracted interface trap charge distribution of the previous study. Logic circuits, such as inverters (INVs), ring oscillators (ROs), a 2 to 1 multiplexer (MUX), and D flip-flop and 6-transistor static random-access memory (6T SRAM) containing M3DINVs, were simulated using the extracted model parameters, and simulation results both with and without interface trap charges were compared. The extracted model parameters reflected current reduction, threshold voltage increase, and subthreshold swing (SS) degradation due to the interface trap charge. HSPICE simulation results of the fanout-3 (FO3) ring oscillator considering the interface trap charges showed a 20% reduction in frequency and a 30% increase in propagation delay compared to those without the interface trap charges. The propagation delays of the 2 × 1 MUX and D flip-flop with the interface trap charges were approximately 78.2 and 39.6% greater, respectively, than those without the interface trap charges. The retention static noise margin (SNM) of the SRAM increased by 16 mV (6.4%) and the read static noise margin (SNM) of SRAM decreased by 43 mV (35.8%) owing to the interface trap charge. The circuit simulation results revealed that the propagation delay increases owing to the interface trap charges. Therefore, it is necessary to fully consider the propagation delay of the logic circuit due to the generated interface trap charges when designing monolithic 3D integrated circuits.

Reconstructing a quantum state with a variational autoencoder

Quantum state tomography (QST) is an important and challenging task in the field of quantum information, which has attracted a lot of attentions in recent years. Machine learning models can provide a classical representation of the quantum state after trained on the measurement outcomes, which are part of effective techniques to solve QST problem. In this work, we use a variational autoencoder (VAE) to learn the measurement distribution of two quantum states generated by MPS circuits. We first consider the Greenberger–Horne–Zeilinger (GHZ) state which can be generated by a simple MPS circuit. Simulation results show that a VAE can reconstruct 3- to 8-qubit GHZ states with a high fidelity, i.e., 0.99, and is robust to depolarizing noise. The minimum number ([Formula: see text]) of training samples required to reconstruct the GHZ state up to 0.99 fidelity scales approximately linearly with the number of qubits ([Formula: see text]). However, for the quantum state generated by a complex MPS circuit, [Formula: see text] increases exponentially with [Formula: see text], especially for the quantum state with high entanglement entropy.

Study of coloured anodized coatings on aluminum alloy by electrochemical impedance spectroscopy

Anodizing, porous anodic alumina, electrochemical impedance spectroscopy, electrolytic coloring, hydrothermal sealing, equivalent electrical circuit, simulation.