Review of Physically Unclonable Functions (PUFs): Structures, Models, and Algorithms

Physically unclonable functions (PUFs) are now an essential component for strengthening the security of Internet of Things (IoT) edge devices. These devices are an important component in many infrastructure systems such as telehealth, commerce, industry, etc. Traditionally these devices are the weakest link in the security of the system since they have limited storage, processing, and energy resources. Furthermore they are located in unsecured environments and could easily be the target of tampering and various types of attacks. We review in this work the structure of most salient types of PUF systems such as static RAM static random access memory (SRAM), ring oscillator (RO), arbiter PUFs, coating PUFs and dynamic RAM dynamic random access memory (DRAM). We discuss statistical models for the five most common types of PUFs and identify the main parameters defining their performance. We review some of the most recent algorithms that can be used to provide stable authentication and secret key generation without having to use helper data or secure sketch algorithms. Finally we provide results showing the performance of these devices and how they depend on the authentication algorithm used and the main system parameters.

A Novel 8T Cell-Based Subthreshold Static RAM for Ultra-Low Power Platform Applications

Subthreshold SRAMs profit various energy-constrained applications. The traditional 6T SRAMs exhibit poor cell stability with voltage scaling. To this end, several 8T to 16T cell designs have been reported to improve the stability. However, they either suffer one of disturbances or consume large bit-area overhead. Furthermore, some cell options have a limited write-ability. This paper presents a novel 8T static RAM for reliable subthreshold operation. The cell employs a fully differential scheme and features cross-point access. An adaptive cell bias for each operating mode eliminates the read disturbance and enlarges the write-ability as well as the half-select stability in a cost-effective small bit-area. The bit-cell also can support efficient bit-interleaving. To verify the SRAM technique, a 32-kbit macro incorporating the proposed cell was implemented with an industrial 180 nm low-power CMOS process. At 0.4 V and room temperature, the proposed cell achieves 3.6× better write-ability and 2.6× higher dummy-read stability compared with the commercialized 8T cell. The 32-kbit SRAM successfully operates down to 0.21 V (~0.27 V lower than transistor threshold voltage). At its lowest operating voltage, the sleep-mode leakage power of entire SRAM is 7.75 nW. Many design results indicate that the proposed SRAM design, which is applicable to an aggressively-scaled process, might be quite useful in realizing cost-effective robust ultra-low voltage SRAMs.

Design of Low Power 6T Sram with and without ROFs

An aggressive scaling in size and the increasing number of the transistor count are the important challenge of the design of Integrated Circuit (IC). In the same manner interconnection lines and resistive opens also became a major problem in present nanometer technology. The resistive open faults [ROFs] represent degradation [1] in connectivity’s within a circuit’s interconnections because of unavoidable manufacturing failures present in both current and future developing technologies. The resistive open fault [ROF] is an imperfect circuit connection that can be modelled as a defect resistors between two nodes of the circuit. The Resistive open faults [2] not causes the functionality of the circuit instantly. But, it causes the delay faults. In this research proposal, the impact of resistive open faults measured in 6-Transistors (6T) Static RAM memory cell design. The proposed 6T Static RAM memory cell implemented in 45nm technology by using Cadence Virtuoso library. The main goal of this proposed research work is to analise the effect of resistive open faults and how it reduce delay and power of 6T Static RAM cell. The resultant outputs of proposed 6T SRAM cell operation with and without ROFs will be compared.

A Low Power 6T-Auto Awake Mode-SRAM Design for high speed storage application

In the digital world, Static Random Access Memory (SRAM) is one of the efficient core component for electronics design, it consumes huge amount of power and die area. In this research, the SRAM design analysis in terms of read margin, write margin and Static Noise Margin (SNM) for low power application is considered. In SRAM memory, both read and write operation affect by noise margin. So, read and write noise margins are considered as the significant challenges in designing SRAM cell. In this research, robust 6T-SRAM cell is designed to decrease the power utilization. The Auto Awake Mode is developed to control the entire 6T-SRAM cell design. The proposed 6T-SRAM- Auto Awake Mode (6T-SRAM-AAM) was implemented to reduce power utilization of understand and write down operation inside the 20 nm FinFET library. The experimental results showed the proposed 6T-SRAM-AAM design reduced power consumption of read & write operation up to 25% to 33.33% compared to existing Static RAM cells design

Modeling the Power Consumption of Function-Level Code Relocation for Low-Power Embedded Systems

The problems associated with the battery life of embedded systems were addressed by focusing on memory components that are heterogeneous and are known to meaningfully affect the power consumption and have not been fully exploited thus far. Our study establishes a model that predicts and orders the efficiency of function-level code relocation. This is based on extensive code profiling that was performed on an actual system to discover the impact and was achieved by using function-level code relocation between the different types of memory, i.e., flash memory and static RAM, to reduce the power consumption. This was accomplished by grouping the assembly instructions to evaluate the distinctive power reduction efficiency depending on function code placement. As a result of the profiling, the efficiency of the function-level code relocation was the lowest at 11.517% for the branch and control groups and the highest at 12.623% for the data processing group. Further, we propose a prior relocation-scoring model to estimate the effective relocation order among functions in a program. To demonstrate the effectiveness of the proposed model, benchmarks in the MiBench benchmark suite were selected as case studies. The experimental results are consistent in terms of the scored outputs produced by the proposed model and measured power reduction efficiencies.

Proficient Static RAM design using Sleepy Keeper Leakage Control Transistor & PT-Decoder for handheld application

Due to their large storage capacity and small access time static random access memory (SRAM) has become a vital part in numerous VLSI chips. Low power adequate memory configuration is a standout among the most challenging issues in SRAM design. As the technology node scaling down, leakage power utilization has turned into a noteworthy issue. In this paper a novel power gating technique, namely sleepy keeper leakage control transistor technique (SK-LCT) is proposed for a handheld gadget application. The SRAM architecture has two primary components, specifically SRAM cell and sense amplifier. The proposed SK-LCT technique is applied in both SRAM cell and sense amplifier for a new low power high speed SRAM architecture design. The outline of SRAM architecture utilizing pass transistor decoder (PT-Decoder) gives better outcomes in term of power. Simulation is done using Tanner EDA tool in 180nm technology and the results demonstrate a noteworthy change in leakage power utilization and speed.

Open-Hardware and Application Specific Design for the Monitoring System of the Belle II Forward/Backward Electromagnetic Calorimeter

Control and monitoring of experimental facilities as well as laboratory equipment requires handling a blend of different tasks. Often in industrial or scientific fields there are standards or form factor to comply with and electronic interfaces or custom busses to adopt. With such tight boundary conditions, the integration of an off-the-shelf Single Board Computer (SBC) is not always a possible or viable alternative. The availability of electronic schematics and PCBs with open-source Hardware license for various SBCs overcomes such integration problems, making feasible the implementation of a custom architecture composed by a central core inherited from a vendor reference design (most likely the microprocessor, static RAM and flash memory) augmented with application-specific integrated circuits and hardware resources, in order to handle the requirements of the specific environment. The user is then able to exploit most of the supported tools and software provided by opensource community, fulfilling all the constraints enforced by his environment. We have used such an approach for the design and development of the monitoring system of the endcap electromagnetic calorimeter of the Belle II experiment, presently running at KEK Laboratory (Tsukuba, Japan). Here we present and discuss the main aspects of the hardware architectures and noise performances tailored on the needs of a detector designed around CsI crystal scintillators.

Performance Enhancement of Bidirectional NOC Router With and Without Contention for Reconfigurable Coarse Grained Architecture

<p>Network on Chip (NoC) router plays a vital role in System on Chip (SoC) applications. Routing operation is difficult to perform inside the SoC chip. Because it contains millions of chips in one single Integrated Circuit (IC), in which every chip consists of millions of transistors. Hence NoC router is designed to enable efficient routing operation in the SoC board. NoC router consists of Network Interconnects (NI), Crossbar Switches, arbiters, a routing logic and buffers. Conventional unidirectional router is designed by priority based Round Robin Arbiter (RRA). It produces more delay to find the priority, which comes from various input channels and more area is consumed in unidirectional router. Also if any path failure occurs, it cannot route the data through other output channel. To overcome this problem, a novel bidirectional NoC router with and without contention is proposed, which offers less area and high speed than the existing unidirectional router. A novel bidirectional NoC router consists of round robin arbiter, Static RAM, switch allocator, virtual channel allocator and crossbar switch. The proposed bidirectional router can route the data from any input channel to each and every output channel. So it avoids conflict situation and path failure problems. If any path fails, immediately it will take the alternative path through the switch allocator. The proposed routing scheme is applied into the coarse grained architecture for improving the speed of the interconnection link between two processing elements. Simulation is performed by ModelSim6.3c and synthesis is carried out by Xilinx10.1.</p>