2021 IEEE International Symposium on Circuits and Systems (ISCAS)
Latest Publications

TOTAL DOCUMENTS

750

(FIVE YEARS 750)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

9781728192017

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

A 2.8 nV/√Hz Chopper Amplifier for Bridge Readout with Dual Ripple Reduction and Noise-Nonlinearity -Cancelling Loop

2021 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas51556.2021.9401713 ◽

2021 ◽

Author(s):

Huapin Chen ◽

Lei Zhang ◽

Yan Wang

Keyword(s):

Ripple Reduction ◽

Chopper Amplifier

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1V 4.49nW/Pixel Retinal Prosthesis Chip with Light-to-Stimulus Duration Converter

2021 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas51556.2021.9401380 ◽

2021 ◽

Author(s):

Dong-Hwi Choi ◽

Dong-Woo Jee

Keyword(s):

Stimulus Duration ◽

Retinal Prosthesis

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Design Framework for SRAM-Based Computing-In-Memory Edge CNN Accelerators

2021 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas51556.2021.9401746 ◽

2021 ◽

Author(s):

Yimin Wang ◽

Zhuo Zou ◽

Lirong Zheng

Keyword(s):

Design Framework

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Power Delivery for Silicon Interconnect Fabric

2021 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas51556.2021.9401673 ◽

2021 ◽

Author(s):

Yousef Safari ◽

Boris Vaisband

Keyword(s):

Power Delivery

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Algorithm driven Power-Timing Optimization Methodology for CMOS Digital Circuits considering PVTA Variations

2021 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas51556.2021.9401496 ◽

2021 ◽

Author(s):

Hema Sai Kalluru ◽

Prasenjit Saha ◽

Andleeb Zahra ◽

Zia Abbas

Keyword(s):

Digital Circuits ◽

Timing Optimization ◽

Optimization Methodology

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A Crosstalk-Harnessed Signaling Enhancement that Eliminates Common-Mode Encoding

2021 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas51556.2021.9401463 ◽

2021 ◽

Author(s):

Daniel Iparraguirre ◽

Jose Delgado-Frias ◽

Howard Heck

Keyword(s):

Common Mode

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Monocular Semantic Mapping Based on 3D Cuboids Tracking

2021 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas51556.2021.9401071 ◽

2021 ◽

Author(s):

Xingwu Ji ◽

Zheng Gong ◽

Ruihang Miao ◽

Wuyang Xue ◽

Rendong Ying

Keyword(s):

Semantic Mapping

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Smart-Redundancy: an Alternative SEU/SET Mitigation Method for FPGAs

2021 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas51556.2021.9401092 ◽

2021 ◽

Author(s):

Aurelien Alacchi ◽

Edouard Giacomin ◽

Xifan Tang ◽

Pierre-Emmanuel Gaillardon

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STT-MRAM Architecture with Parallel Accumulator for In-Memory Binary Neural Networks

2021 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas51556.2021.9401695 ◽

2021 ◽

Author(s):

Thi-Nhan Pham ◽

Quang-Kien Trinh ◽

Ik-Joon Chang ◽

Massimo Alioto

Keyword(s):

Neural Networks

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A Process Scalable Architecture for Low Noise Figure Sub-sampling Mixer-First RF Front-End

2021 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas51556.2021.9401387 ◽

2021 ◽

Author(s):

Rakesh Rena ◽

Suraj Kumar Verma ◽

Vijaya Sankara Rao Pasupureddi

Keyword(s):

Noise Figure ◽

Low Noise ◽

Scalable Architecture ◽

Front End ◽

Rf Front End

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2021 IEEE International Symposium on Circuits and Systems (ISCAS)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

A 2.8 nV/√Hz Chopper Amplifier for Bridge Readout with Dual Ripple Reduction and Noise-Nonlinearity -Cancelling Loop

1V 4.49nW/Pixel Retinal Prosthesis Chip with Light-to-Stimulus Duration Converter

Design Framework for SRAM-Based Computing-In-Memory Edge CNN Accelerators

Power Delivery for Silicon Interconnect Fabric

Algorithm driven Power-Timing Optimization Methodology for CMOS Digital Circuits considering PVTA Variations

A Crosstalk-Harnessed Signaling Enhancement that Eliminates Common-Mode Encoding

Monocular Semantic Mapping Based on 3D Cuboids Tracking

Smart-Redundancy: an Alternative SEU/SET Mitigation Method for FPGAs

STT-MRAM Architecture with Parallel Accumulator for In-Memory Binary Neural Networks

A Process Scalable Architecture for Low Noise Figure Sub-sampling Mixer-First RF Front-End

2021 IEEE International Symposium on Circuits and Systems (ISCAS)
Latest Publications