Algorithm driven Power-Timing Optimization Methodology for CMOS Digital Circuits considering PVTA Variations
1987 ◽
Vol 134
(2)
◽
pp. 69
◽
1959 ◽
Vol 106
(16S)
◽
pp. 688-697
◽
Keyword(s):
1988 ◽
Vol 49
(C2)
◽
pp. C2-459-C2-462
◽
Keyword(s):
Keyword(s):
Keyword(s):