Proceedings 18th IEEE VLSI Test Symposium
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62

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0769506135

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Silicon-on-insulator technology impacts on SRAM testing

Proceedings 18th IEEE VLSI Test Symposium ◽

10.1109/vtest.2000.843825 ◽

2002 ◽

Author(s):

R.D. Adams ◽

P. Shephard

Keyword(s):

Silicon On Insulator ◽

Silicon On Insulator Technology

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Cold delay defect screening

Proceedings 18th IEEE VLSI Test Symposium ◽

10.1109/vtest.2000.843843 ◽

2002 ◽

Cited By ~ 20

Author(s):

Chao-Wen Tseng ◽

E.J. Mccluskey ◽

Xiaoping Shao ◽

D.M. Wu

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DEFUSE: a deterministic functional self-test methodology for processors

Proceedings 18th IEEE VLSI Test Symposium ◽

10.1109/vtest.2000.843853 ◽

2002 ◽

Cited By ~ 43

Author(s):

L. Chen ◽

S. Dey

Keyword(s):

Test Methodology ◽

Self Test

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Testability alternatives exploration through functional testing

Proceedings 18th IEEE VLSI Test Symposium ◽

10.1109/vtest.2000.843874 ◽

2002 ◽

Cited By ~ 2

Author(s):

F. Ferrandi ◽

G. Ferrara ◽

G. Fornara ◽

F. Fummi ◽

D. Sciuto

Keyword(s):

Functional Testing

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A rapid and scalable diagnosis scheme for BIST environments with a large number of scan chains

Proceedings 18th IEEE VLSI Test Symposium ◽

10.1109/vtest.2000.843830 ◽

2002 ◽

Cited By ~ 41

Author(s):

J. Ghosh-Dastidar ◽

N.A. Touba

Keyword(s):

Scan Chains

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Extraction of peak-to-peak and RMS sinusoidal jitter using an analytic signal method

Proceedings 18th IEEE VLSI Test Symposium ◽

10.1109/vtest.2000.843870 ◽

2002 ◽

Cited By ~ 30

Author(s):

T.J. Yamaguchi ◽

M. Soma ◽

M. Ishida ◽

T. Watanabe ◽

T. Ohmi

Keyword(s):

Analytic Signal ◽

Signal Method

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Detectability conditions for interconnection open defects

Proceedings 18th IEEE VLSI Test Symposium ◽

10.1109/vtest.2000.843859 ◽

2002 ◽

Cited By ~ 16

Author(s):

V.H. Champac ◽

A. Zenteno

Keyword(s):

Open Defects

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Virtual scan chains: a means for reducing scan length in cores

Proceedings 18th IEEE VLSI Test Symposium ◽

10.1109/vtest.2000.843829 ◽

2002 ◽

Cited By ~ 62

Author(s):

A. Jas ◽

B. Pouya ◽

N.A. Touba

Keyword(s):

Scan Chains ◽

Scan Length

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Synthesis for arithmetic built-in self-test

Proceedings 18th IEEE VLSI Test Symposium ◽

10.1109/vtest.2000.843841 ◽

2002 ◽

Cited By ~ 3

Author(s):

A.P. Stroele

Keyword(s):

Self Test ◽

Built In Self Test

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Clustering based evaluation of I/sub DDQ/ measurements: applications in testing and classification of ICs

Proceedings 18th IEEE VLSI Test Symposium ◽

10.1109/vtest.2000.843877 ◽

2002 ◽

Cited By ~ 7

Author(s):

S. Jandhyala ◽

H. Balachandran ◽

M. Sengupta ◽

A.P. Jayasumana

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