Proceedings of VHDL International Users Forum
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21

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3

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Published By IEEE Computer. Soc. Press

0818662158

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Experiences in testing and debugging the i960 MX VHDL model

Proceedings of VHDL International Users Forum ◽

10.1109/viuf.1994.323957 ◽

2002 ◽

Cited By ~ 3

Author(s):

G.S. Powley ◽

J.E. DeGroat

Keyword(s):

Testing And Debugging

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C to VHDL converter in a codesign environment

Proceedings of VHDL International Users Forum ◽

10.1109/viuf.1994.323960 ◽

2002 ◽

Cited By ~ 3

Author(s):

M.F. Parkinson ◽

P.M. Taylor ◽

S. Parameswaran

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Design of a 16-point Winograd fast Fourier transform algorithm integrated circuit system

Proceedings of VHDL International Users Forum ◽

10.1109/viuf.1994.323958 ◽

2002 ◽

Author(s):

T.S. Wailes ◽

W.D. O'Connor ◽

M.A. Mehalic

Keyword(s):

Fourier Transform ◽

Fast Fourier Transform ◽

Integrated Circuit ◽

Fast Fourier Transform Algorithm

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Integrating hierarchical test benches into an evolving VHDL design environment

Proceedings of VHDL International Users Forum ◽

10.1109/viuf.1994.323963 ◽

2002 ◽

Author(s):

M.F. Sullivan ◽

J.O. Bondi ◽

D.J. Kopca ◽

N.D. Patel

Keyword(s):

Design Environment

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A VHDL synthesis framework

Proceedings of VHDL International Users Forum ◽

10.1109/viuf.1994.323953 ◽

2002 ◽

Author(s):

R.A. Baldwin ◽

Sea Hawon Choi ◽

Moon Jung Chung

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A VHDL based test environment including models for equivalence fault collapsing

Proceedings of VHDL International Users Forum ◽

10.1109/viuf.1994.323969 ◽

2002 ◽

Cited By ~ 3

Author(s):

Z. Navabi ◽

M. Shadfar

Keyword(s):

Test Environment

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VMS: a VHDL Modeling System

Proceedings of VHDL International Users Forum ◽

10.1109/viuf.1994.323965 ◽

2002 ◽

Author(s):

Ch. Lakshmikantam ◽

S. Manohar

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VHDL-based system simulation and performance measurement

Proceedings of VHDL International Users Forum ◽

10.1109/viuf.1994.323966 ◽

2002 ◽

Author(s):

P.A. McCabe

Keyword(s):

Performance Measurement ◽

System Simulation ◽

And Performance

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Hierarchical partitioning of high-level VHDL structures

Proceedings of VHDL International Users Forum ◽

10.1109/viuf.1994.323967 ◽

2002 ◽

Author(s):

T. Karnik ◽

Sung-Mo Kang

Keyword(s):

Hierarchical Partitioning ◽

High Level

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A VHDL based environment for system level design and analysis

Proceedings of VHDL International Users Forum ◽

10.1109/viuf.1994.323959 ◽

2002 ◽

Cited By ~ 6

Author(s):

G. Swaminathan ◽

R. Rao ◽

J.H. Aylor ◽

B.W. Johnson

Keyword(s):

System Level ◽

System Level Design ◽

Level Design

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