Characterization of electrostatic discharge threshold voltage of phase-shift mask reticle

A reticle is a stencil used in lithography process for forming integrated circuit (IC) on silicon substrate. It consists of a thin (100 nm) coating of masking metallic patterned (features) with critical dimension (CD) of nanometers on a thicker quartz substrate. The features can be damaged by electrostatic discharge (ESD) when exposed to the environment electrostatic charge and caused deformed IC and eventually device difunctional. Semiconductor equipment materials industry (SEMI) standard established the allowable electrostatic charge on reticle based on the characterization of ESD threshold voltage on binary reticle. However, there is another type of reticle which is phase-shift mask (PSM), has not been characterized for its ESD threshold voltage. A direct current (DC) voltage is applied directly to the structures with CD of 80 nm, 110 nm, and 160 nm. The surface current is recorded at all levels of stress from 1 to 100 V. The current–voltage (IV) curve and physical inspection results for each cell are then reviewed and classified. The results yielded which no electric field induced migration (EFM) defect and breakdown voltage occurred at any of the structures. The cathode’s metal work function has been identified as the factor that influences the PSM reticle ESD threshold voltage.

Inductanceless high order low frequency filters for medical applications

<p>In this paper, a designed circuit used for low-frequency filters is implemented and realized the filter is based on frequency-dependent negative resistance (FDNR) as an inductor simulator to substitute the traditional inductance, which is heavy and high cost due to the coil material manufacturing and size area. The simulator is based on an active operation amplifier or operation transconductance amplifier (OTA) that is easy to build in an integrated circuit with a minimum number of components. The third and higher-order Butterworth filter is simulated at low frequency for low pass filter to use in medical instruments and low-frequency applications. The designed circuit is compared with the traditional proportional integral controller enhanced (PIE) and T section ordinary filter. The results with magnitude and phase response were compared and an acceptable result is obtained. The filter can be used for general applications such as medical and other low-frequency filters needed.</p>

The voltage-mode first order universal filter using single voltage differencing differential input buffered amplifier with electronic controllability

In this research contribution, the electronically tunable first-order universal filter employing a single voltage differencing differential input buffered amplifier (VD-DIBA) (constructed from two commercially available integrated circuit (IC): the operational transconductance amplifier, IC number LT1228, and the differential voltage input buffer, IC number AD830), one capacitor and two resistors. The features of the designed first order universal filter are as follows. Three voltage-mode first-order functions, low-pass (LP), all-pass (AP) and high-pass (HP) responses are given. The natural frequency (𝜔0) of the presented configuration can be electronically adjusted by setting the DC bias current. Moreover, the voltage gain of the LP and HP filters can be controllable. The phase responses of an AP configuration can be varied from 00 to −1800 and 1800 to 00. The power supply voltages were set at ±5 𝑉. Verification of the theoretically described performances of the introduced electronically tunable universal filter was proved by the PSpice simulation and experiment.

Dynamic Optimization of Bus Line Schedule in Commuter Corridor Based on Bus IC Card Data

The aim of this study was to explore the bus operating state of the city bus passenger corridor, taking the minimum bus operating cost and passenger travel cost as the objective function, taking passenger flow demand and operating income as the constraint, and considering the average speed change of the bus line in the bus corridor at different times. This paper proposes a dynamic optimization model of bus route schedule based on bus Integrated Circuit Card (IC Card) data. The optimization variable is the departure frequency of the candidate lines. To solve the model, a dynamic departure interval optimization method based on improved Genetic Algorithm (GA) was designed under different decision preferences. The method includes the calibration of generalized cost functions for passengers and bus companies and grasps the characteristics of bus operating speed changes and the design of departure strategies under different decision preferences. The validity and applicability of the proposed method are verified by a numerical example. We mainly carried out the following work: (1) Dynamic analysis of the time dimension of the bus departure interval takes into account the changes in passenger time characteristics during peak periods. (2) Seven schemes of weight ratio of passenger waiting time cost and bus operation cost were designed, and the departure intervals with different benefit orientations of passengers and operators were discussed, respectively, so as to select the corresponding departure schemes for decision makers under different decision preferences. The results show that (1) the total cost of the 7 different weighting schemes is lower than the actual value by 6.90% to 18.20%; (2) when decision makers need to bias the weight to the bus company, the weight ratio α : β between passengers and bus company is 0.25 : 0.75 which works best. The frequency of departures has been reduced by 6, and at the same time, the total optimized cost is reduced by 18.2%; (3) when decision makers need to bias the weight to the passengers, the weight ratio α : β between the passengers and bus company is 0.75 : 0.25 which works best. The frequency of departures has been increased by 19, and at the same time, the total optimized cost is reduced by 17.7%; and (4) when decision makers consider passengers and bus companies equally, the weight ratio α : β between passengers and bus companies is 0.5 : 0.5, the optimization cost is the closest to the actual cost, the optimization cost is reduced by 6.9%, and the frequency of departures has been increased by 5. The results show that the model in this paper provides a new idea for the information mining of bus routes in the research based on the bus IC Card data and provides an effective tool for the management of different operation decision preferences.

Multipurpose Bio-Monitored Integrated Circuit in a Contact Lens Eye-Tracker

We present the design, fabrication, and test of a multipurpose integrated circuit (Application Specific Integrated Circuit) in AMS 0.35 µm Complementary Metal Oxide Semiconductor technology. This circuit is embedded in a scleral contact lens, combined with photodiodes enabling the gaze direction detection when illuminated and wirelessly powered by an eyewear. The gaze direction is determined by means of a centroid computation from the measured photocurrents. The ASIC is used simultaneously to detect specific eye blinking sequences to validate target designations, for instance. Experimental measurements and validation are performed on a scleral contact lens prototype integrating four infrared photodiodes, mounted on a mock-up eyeball, and combined with an artificial eyelid. The eye-tracker has an accuracy of 0.2°, i.e., 2.5 times better than current mobile video-based eye-trackers, and is robust with respect to process variations, operating time, and supply voltage. Variations of the computed gaze direction transmitted to the eyewear, when the eyelid moves, are detected and can be interpreted as commands based on blink duration or using blinks alternation on both eyes.

Meander-DGS Effect on Electromagnetic Bandgap Structure for Power/Ground Noise Suppression in High-Speed Integrated Circuit Packages and PCBs

In this paper, we present the impact of a meander-shaped defected ground structure (MDGS) on the slow-wave characteristics of a lowest-order passband and a low cutoff frequency of the first stopband of an electromagnetic bandgap (EBG) structure for power/ground noise suppression in high-speed integrated circuit packages and printed circuit boards (PCBs). A semi-analytical method is presented to rigorously analyze the MDGS effect. In the analytical method, a closed-form expression for a low cutoff frequency of the MDGS-EBG structure is extracted with an effective characteristic impedance and a slow-wave factor. The proposed analytical method enables the fast analysis of the MDGS-EBG structure so that it can be easily optimized. The analysis of the MDGS effect revealed that the low cutoff frequency increases up to approximately 19% while comparing weakly and strongly coupled MDGSs. It showed that the miniaturization of the MDGS-EBG structure can be achieved. It was experimentally verified that the low cutoff frequency is reduced from 2.54 GHz to 2.00 GHz by decreasing the MDGS coupling coefficient, which is associated with the miniaturization of the MDGS-EBG structure in high-speed packages and PCBs.

Design of a Fully Integrated VHF CP-PLL Frequency Synthesizer with an All-Digital Defect-Oriented Built-In Self-Test.

This paper presents the design of an on-chip charge pump phase-locked loop (CP-PLL) with a fully digital defect oriented built-in self-test (BIST) for very-high frequency (VHF) applications. The frequency synthesizer has a 40 to 100 MHz tuning range and uses a ring voltage-controlled oscillator for frequency synthesis. The PLL exhibits a phase noise of -132 dBc/Hz at 1 MHz and consumes 1.8 mW on a 3 V supply. The BIST implementation uses fewer external input or output, is capable of efficient fault diagnosis, and is compact, posing a low area overhead. The integrated circuit design was realized in the AMI 0.6µ complementary metal oxide-semiconductor process.

Electronically Adjustable Grounded Memcapacitor Emulator Based on Single Active Component with Variable Switching Mechanism

New current mode grounded memcapacitor emulator circuits are reported in this paper, based on a single voltage differencing transconductance amplifier-VDTA and two grounded capacitors. The proposed circuits possess a single active component matching constraint, while the MOS-capacitance can be used instead of classical capacitance in a situation involving the simulator working within a high frequency range of up to 50 MHz, thereby offering obvious benefits in terms of realization utilising an IC-integrated circuit. The proposed emulator offers a variable switching mechanism—soft and hard—as well as the possibility of generating a negative memcapacitance characteristic, depending on the value of the frequency of the input current signal and the applied capacitance. The influence of possible non-ideality and parasitic effects was analysed, in order to reduce their side effects and bring the outcome to acceptable limits through the selection of passive elements. For the verification purposes, a PSPICE simulation environment with CMOS 0.18 μm TSMC technology parameters was selected. An experimental check was performed with off-the-shelf components-IC MAX435, showing satisfactory agreement with theoretical assumptions and conclusions.

Single Stage Active Power Factor Correction Circuit for Street LED Light with Battery Backup

This paper introduces and uses a single-phase, high-power LED driver with a battery backup. The buck–boost converter and reverse converter are both combined to achieve optimal performance. In the first part of the integrated circuit, the buck–boost converter is simply used to adjust the power when operating in the non-continuous operating mode. The reverse converter provides free voltage to the LEDs when released as a remote DC–DC converter. The battery backup cycle directly charges the battery at the same power as the LED driver required and provides charging power when there is no electricity. This paper demonstrates the functionality of the entire system and proves that it is an effective solution for new lighting applications.

Pixel readout IC for CdTe detectors operating in single photon counting mode with interpixel communication

This paper presents a readout integrated circuit (IC) of pixel architecture called MPIX (Multithreshold PIXels), designed for CdTe pixel detectors used in X-ray imaging applications. The MPIX IC area is 9.6 mm × 20.3 mm and it is designed in a CMOS 130 nm process. The IC core is a matrix of 96 × 192 square-shaped pixels of 100 µm pitch. Each pixel contains a fast analog front-end followed by four independently working discriminators and four 12-bit ripple counters. Such pixel architecture allows photon processing one by one and selecting the X-ray photons according to their energy (X-ray colour imaging). To fit the different range of applications the MPIX IC has 8 possible different gain settings, and it can process the X-ray photons of energy up to 154 keV. The MPIX chip is bump-bonded to the CdTe 1.5 mm thick pixel sensor with a pixel pitch of 100 µm. To deal with the charge sharing effect coming from a thick semiconductor pixel sensor, multithreshold pattern recognition algorithm is implemented in the readout IC. The implemented algorithm operates both in the analog domain (to recover the total charge spread between neighboring pixels, when a single X-ray photon hits the border of the pixel) and in the digital domain (to allocate a hit position to a single pixel).