2011 Electronic System Level Synthesis Conference (ESLsyn)
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Published By IEEE

9781457706349

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2011 Electronic System Level Synthesis Conference (ESLsyn) ◽

10.1109/eslsyn.2011.5952275 ◽

2011 ◽

Session 1: Co-design — Part I

2011 Electronic System Level Synthesis Conference (ESLsyn) ◽

10.1109/eslsyn.2011.5952278 ◽

2011 ◽

Author(s):

Thierry Gauthier

From design-time concurrency to effective implementation parallelism: The multi-clock reactive case

2011 Electronic System Level Synthesis Conference (ESLsyn) ◽

10.1109/eslsyn.2011.5952287 ◽

2011 ◽

Cited By ~ 5

Author(s):

V. Papailiopoulou ◽

D. Potop-Butucaru ◽

Y. Sorel ◽

R. de Simone ◽

L. Besnard ◽

...

Keyword(s):

Effective Implementation ◽

Design Time

Increasing computational density of application-specific systems

2011 Electronic System Level Synthesis Conference (ESLsyn) ◽

10.1109/eslsyn.2011.5952293 ◽

2011 ◽

Author(s):

Michael D. Wilder ◽

Robert E. Rinker

Keyword(s):

Application Specific

Front cover

2011 Electronic System Level Synthesis Conference (ESLsyn) ◽

10.1109/eslsyn.2011.5952273 ◽

2011 ◽

Keyword(s):

Front Cover

Title page

2011 Electronic System Level Synthesis Conference (ESLsyn) ◽

10.1109/eslsyn.2011.5952274 ◽

2011 ◽

Keyword(s):

Title Page

Just-in-time compilation for FPGA processor cores

2011 Electronic System Level Synthesis Conference (ESLsyn) ◽

10.1109/eslsyn.2011.5952282 ◽

2011 ◽

Cited By ~ 1

Author(s):

Andrew Becker ◽

Scott Sirowy ◽

Frank Vahid

Keyword(s):

Just In Time ◽

Processor Cores

Session 3: Modelling

2011 Electronic System Level Synthesis Conference (ESLsyn) ◽

10.1109/eslsyn.2011.5952284 ◽

2011 ◽

Author(s):

Yuko Hara-Azumi

Session 4: Co-design — Part II

2011 Electronic System Level Synthesis Conference (ESLsyn) ◽

10.1109/eslsyn.2011.5952288 ◽

2011 ◽

Kahn process networks applied to distributed heterogeneous HW/SW cosimulation

2011 Electronic System Level Synthesis Conference (ESLsyn) ◽

10.1109/eslsyn.2011.5952290 ◽

2011 ◽

Cited By ~ 5

Author(s):

Dylan Pfeifer ◽

Jonathan Valvano

Keyword(s):

Process Networks ◽

Kahn Process

2011 Electronic System Level Synthesis Conference (ESLsyn)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Copyright page

Session 1: Co-design — Part I

From design-time concurrency to effective implementation parallelism: The multi-clock reactive case

Increasing computational density of application-specific systems

Front cover

Title page

Just-in-time compilation for FPGA processor cores

Session 3: Modelling

Session 4: Co-design — Part II

Kahn process networks applied to distributed heterogeneous HW/SW cosimulation

2011 Electronic System Level Synthesis Conference (ESLsyn)
Latest Publications