Means and Methods of Efficiency Estimation of Video Stream Transmission Based on GigE Vision Technology Using Application Processor

The paper investigates the possibility of efficient implementation of a GigE Vision compatible video stream source on a computing platform based on a system-on-a-chip with general-purpose ARM processor cores. In particular, to implement the aforementioned video source, a proprietary prototype of a GigE Vision compatible camera was developed based on the Raspberry Pi 4 single-board computer. This computing platform was chosen due to its widespread use and wide community support. The software part of the camera is implemented using the Video4Linux and Aravis libraries. The first library is used for the primary image capturing from a video sensor connected to a single board computer. The second library is intended for forming and transmission of video stream frames compatible with GigE Vision technology over the network. To estimate the delays in the transmission of a video stream over an Ethernet channel, a methodology based on the Precise Time Protocol (PTP) has been proposed and applied. During the experiments, it was found that the software implementation of a GigE Vision compatible camera on single-board computers with general-purpose processor cores is quite promising. Without additional optimization, such an implementation can be successfully used to transmit small frames (with a resolution of up to 640 × 480 pixels), giving a delay less than 10 ms. At the same time, some additional optimizations may be required to transmit larger frames. Namely, a MTU (maximum transmission unit) size value plays the crucial role in latency formation. Thus, to implement a faster camera, it is necessary to select a platform that supports the largest possible MTU (unfortunately, it turned out that it is not possible with Raspberry Pi 4, as it supports relatively small MTU size of up to 2000 bytes). In addition, the image format conversion procedure can noticeably affect the delay. Therefore, it is highly desirable to avoid any frame processing on the transmitter side and, if it is possible, to broadcast raw images. If the conversion of the frame format is necessary, the platform should be chosen so that there are free computing cores on it, which will permit to distribute all necessary frame conversions between these cores using parallelization techniques.

Attacking TrustZone on devices lacking memory protection

ARM TrustZone offers a Trusted Execution Environment (TEE) embedded into the processor cores. Some vendors offer ARM modules that do not fully comply with TrustZone specifications, which may lead to vulnerabilities in the system. In this paper, we present a DMA attack tutorial from the insecure world onto the secure world, and the design and implementation of this attack in a real insecure hardware.

The list algorithms accuracy characteristics improvement based on Krohn’s algorithm and its modifications

The research of algorithms for uniform loading of devices for homogeneous information processing systems is a very important science-intensive task. An experimental approach was chosen for the research. This is primarily due to the fact that the analytical solution of the distribution problem gives solutions that are far from reality, since it is unable to take into account many factors that affect the computing machine during its operation. The aim of this research is to improve the accuracy characteristics of the list algorithms through the use of heuristic algorithms, such as Krohn’s algorithm and its modifications. This made it possible to obtain a more even distribution of tasks among executive devices, which can be networked workstations, processors or processor cores. The work uses list algorithms, such as the Critical Path algorithm and Pashkeev’s algorithm, as well as heuristic algorithms - Krohn’s algorithm and its modifications. The main idea of the research is to obtain the best suboptimal solution by improving the quality of the resulting distribution. In this case, with the help of the list algorithms, the initial distribution is formed, and its refinement is carried out through the application of the Krohn’s algorithm and its modifications. In fact, in the work, a number of symbiotic algorithms are examined and analyzed. For this, many computational experiments were carried out and a large amount of output data were collected, on the basis of which conclusions were drawn about the effectiveness of the solution obtained for each symbiotic group and for all groups as a whole.

Optimal Reduction in the Number of Test Vectors for Soft Processor Cores Implemented in FPGA

Testing FPGA-based soft processor cores requires a completely different methodology in comparison to standard processors. The stuck-at fault model is insufficient, as the logic is implemented by lookup tables (LUTs) in FPGA, and this SRAM-based LUT memory is vulnerable to single-event upset (SEU) mainly caused by cosmic radiations. Consequently, in this paper, we used combined SEU-induced and stuck-at fault models to simulate every possible fault. The test program written in an assembler was based on the bijective property. Furthermore, the fault detection matrix was determined, and this matrix describes the detectability of every fault by every test vector. The major novelty of this paper is the optimal reduction in the number of required test vectors in such a way that fault coverage is not reduced. Furthermore, this paper also studied the optimal selection of test vectors when only 95% maximal fault coverage is acceptable; in such a case, only three test vectors are required. Further, local and global test vector selection is also described.

Optimal Reduction of Number of Test Vectors for Soft Processor Cores Implemented in FPGA

This paper describes a new optimization methodology of testing vector sets reduction for testing of soft-processor cores and their individual blocks. The deterministic test vectors both for whole core and its individual blocks are investigated that significantly reduce the testing time and amount of test data that needs to be stored on the tester memory. The processor executes an assembler program which together with determined testing vectors ex-ercise its functionality. The new BIST methodology applicable at industrial testing of processor cores, diagnostics and dynamic reconfiguration of FPGA is proposed. This novel methodology combined with dynamic reconfiguration of FPGAs can be profitable applied for missions-critical i.e. FPGAs operate in space, or other difficult condition where are explore on radiation. Experimental results demonstrate that the proposed approach reduces many times testing time.

High Priority Arbitration for Less Burst Data Transactions for Improved Average Waiting Time of Multi-Processor Cores

The multi-processor cores in SoC which have high burst data transactions can play a critical role while accessing the shared resources such as the off-chip memory. These processor cores can starve other processor cores that have less burst data transactions while accessing the same shared resources. The starving issue of other processor cores leads to degrade the entire system performance of the SoC. However, the arbiter architecture in the SoC design plays the best solution to manage different processor core requests and granting one of them to access the shared resources according to different scheduling algorithms. In this paper, we have designed AXI interconnect, which includes arbiter architecture to connect four processor cores represented by the AXI masters and the off-chip memory represented by the salve. Each processor core (AXI Master) uses the AXI4 interface protocol to improve the system performance and the arbiter based on the static fixed-priority algorithm to improve the average waiting time for all the processor cores. The SoC design architecture is modeled in System Verilog HDL; simulation and synthesis are done by using the Vivado tool and FPGA ZYNQ-7 ZC702 Evaluation Board (xc7z020clg484-1).

DESIGN OF FIR FILTER ALGORITHM FOR NOISE REMOVAL IN ECG SIGNAL USING OPEN CORE SoC

The emerging technology in computer architecture has led to the development of various ISAs depending on the needs of the desired technology, architectures, and processor cores. Instruction Set Architectures (ISAs) for processors from Intel, AMD, Intel, RISC-V, etc. This has provided the path to implement various functions on an open core SoC Platform. Among the many DSP applications, the FIR filter has been implemented on an open core SoC platform that uses RISCV. Here specifically filtering of noise from ECG signal. The performance cycle count has been obtained for the same and compared with its counterpart ARM M7 on the Keil platform.

The Optimal Processor Cores' Number choice for the Parallel Cluster Multiple Labeling Technique on HighPerformance Computing Systems

The article is about the research of a optimum number of processor cores for launching the Parallel Cluster Multiple Labeling Technique on modern supercomputer systems installed in the JSCC RAS. This technique may be used in any field as a tool for differentiating large lattice clusters, because it is given input in a format independent of the application. At the JSCC RAS, this tool was used to study the problem of the spread of epidemics, for which an appropriate multiagent model was developed. In the course of imitation experiments, a variant of the Parallel Cluster Multiple Labeling Technique for percolation Hoshen-Kopelman clusters related to the tag linking mechanism, which can also be used in any area as a tool for differentiating large-size lattice clusters, was used to be improved on a multiprocessor system.