Design and Deployment of Expressive and Correct Web of Things Applications

Consumer Internet of Things (IoT) applications are largely built through end-user programming in the form of event-action rules. Although end-user tools help simplify the building of IoT applications to a large extent, there are still challenges in developing expressive applications in a simple yet correct fashion. In this context, we propose a formal development framework based on the Web of Things specification. An application is defined using a composition language that allows users to compose the basic event-action rules to express complex scenarios. It is transformed into a formal specification that serves as the input for formal analysis, where the application is checked for functional and quantitative properties at design time using model checking techniques. Once the application is validated, it can be deployed and the rules are executed following the composition language semantics. We have implemented these proposals in a tool built on top of the Mozilla WebThings platform. The steps from design to deployment were validated on real-world applications.

Bug Localization in Model-Based Systems in the Wild

The companies that have adopted the Model-Driven Engineering (MDE) paradigm have the advantage of working at a high level of abstraction. Nevertheless, they have the disadvantage of the lack of tools available to perform bug localization at the model level. In addition, in an MDE context, a bug can be related to different MDE artefacts, such as design-time models, model transformations, or run-time models. Starting the bug localization in the wrong place or with the wrong tool can lead to a result that is unsatisfactory. We evaluate how to apply the existing model-based approaches in order to mitigate the effect of starting the localization in the wrong place. We also take into account that software engineers can refine the results at different stages. In our evaluation, we compare different combinations of the application of bug localization approaches and human refinement. The combination of our approaches plus manual refinement obtains the best results. We performed a statistical analysis to provide evidence of the significance of the results. The conclusions obtained from this evaluation are: humans have to be involved at the right time in the process (or results can even get worse), and artefact-independence can be achieved without worsening the results.

Intelligent Analysis of Computer-Aided Garment Design CAD Based on Virtual Reality Model for Surplus Fabric Removal and Reuse without Segmentation of Cutting Pieces

For the purpose of improving the efficiency of garment design, the computer-aided garment design virtual reality (VR) model for surplus fabric removal and reuse without segmentation of cutting pieces is analyzed in this paper to provide the architecture of the computer-aided garment design CAD system. The form of dividing the garment into multiple types of nonsegmented pieces is adopted so that each nonsegmented piece stands for a complete design element unit. Based on this structure, the computer analysis of garment design based on CAD can be connected at a deeper level, which will not only improve the design efficiency of new garments but also reduce the design time at the client terminal and enhance the quality of the design. Through the experimental operation of prototypes, it is verified that the intelligent system proposed in this paper can implement the design of prototypes quickly and effectively.

Optimal Design of a BLDC Motor Considering Three-Dimensional Structures Using the Response Surface Methodology

In this paper, the optimal design of a brushless direct current motor with a three-dimensional (3D) structure using the response surface methodology (RSM) is presented. There were two optimization goals: reduction of the cogging torque and maintenance of the back electromotive force to prevent performance degradation. For motors with a 3D structure, a 3D finite element method analysis is essential, though it requires considerable computation time. Therefore, to reduce the optimal design time, the 3D structure was placed on the 2D plane. Thereafter, a 2D corrected model was applied to the RSM. For the validity of the technique, the analysis results of the initial 3D model, 2D model, and 2D corrected model were compared, and the results of the optimal design 3D model, 2D corrected model, and experiment were compared.

Adaptive Scheduling for Time-Triggered Network-on-Chip-Based Multi-Core Architecture Using Genetic Algorithm

Adaptation in time-triggered systems can be motivated by energy efficiency, fault recovery, and changing environmental conditions. Adaptation in time-triggered systems is achieved by preserving temporal predictability through metascheduling techniques. Nevertheless, utilising existing metascheduling schemes for time-triggered network-on-chip architectures poses design time computation and run-time storage challenges for adaptation using the resulting schedules. In this work, an algorithm for path reconvergence in a multi-schedule graph, enabled by a reconvergence horizon, is presented to manage the state-space explosion problem resulting from an increase in the number of scenarios required for adaptation. A meta-scheduler invokes a genetic algorithm to solve a new scheduling problem for each adaptation scenario, resulting in a multi-schedule graph. Finally, repeated nodes of the multi-schedule graph are merged, and further exploration of paths is terminated. The proposed algorithm is evaluated using various application model sizes and different horizon configurations. Results show up to 56% reduction of schedules necessary for adaptation to 10 context events, with the reconvergence horizon set to 50 time units. Furthermore, 10 jobs with 10 slack events and a horizon of 40 ticks result in a 23% average sleep time for energy savings. Furthermore, the results demonstrate the reduction in the state-space size while showing the trade-off between the size of the reconvergence horizon and the number of nodes of the multi-schedule graph.

Design of Secure Microcontroller-Based Systems: Application to Mobile Robots for Perimeter Monitoring

This paper describes an original methodology for the design of microcontroller-based physical security systems and its application for the system of mobile robots. The novelty of the proposed methodology lies in combining various design algorithms on the basis of abstract and detailed system representations. The suggested design approach, which is based on the methodology, is modular and extensible, takes into account the security of the physical layer of the system, works with the abstract system representation and is looking for a trade-off between the security of the final solution and the resources expended on it. Moreover, unlike existing solutions, the methodology has a strong focus on security. It is aimed at ensuring the protection of the system against attacks at the design stage, considers security components as an integral part of the system and checks if the system can be designed in accordance with given requirements and limitations. An experimental evaluation of the methodology was conducted with help of its software implementation that consists of Python script, PostgreSQL database, Tkinter interface and available for download on our GitHub. As a use case, the system of mobile robots for perimeter monitoring was chosen. During the experimental evaluation, the design time was measured depending on the parameters of the attacker against which system security must be ensured. Moreover, the software implementation of the methodology was analyzed in compliance with requirements and compared with analogues. The advantages and disadvantages of the methodology as well as future work directions are indicated.

Ontology Versioning Driven by Instance Evolution in the τOWL Framework

Like other components of Semantic Web-based applications, ontologies are evolving over time to reflect changes in the real world. Several of these applications require keeping a full-fledged history of ontology changes so that both ontology instance versions and their corresponding ontology schema versions are maintained. Updates to an ontology instance could be non-conservative that is leading to a new ontology instance version no longer conforming to the current ontology schema version. If, for some reasons, a non-conservative update has to be executed, in spite of its consequence, it requires the production of a new ontology schema version to which the new ontology instance version is conformant so that the new ontology version produced by the update is globally consistent. In this paper, we first propose an approach that supports ontology schema changes which are triggered by non-conservative updates to ontology instances and, thus, gives rise to an ontology schema versioning driven by instance updates. Note that in an engineering perspective, such an approach can be used as an incremental ontology construction method driven by the modification of instance data, whose exact structure may not be completely known at the initial design time. After that, we apply our proposal to the already established [Formula: see text]OWL (Temporal OWL 2) framework, which allows defining and evolving temporal OWL 2 ontologies in an environment that supports temporal versioning of both ontology instances and ontology schemas, by extending it to also support the management of non-conservative updates to ontology instance versions. Last, we show the feasibility of our approach by dealing with its implementation within a new release of the [Formula: see text] OWL-Manager tool.

An FPGA-Based LOCO-ANS Implementation for Lossless and Near-Lossless Image Compression Using High-Level Synthesis

In this work, we present and evaluate a hardware architecture for the LOCO-ANS (Low Complexity Lossless Compression with Asymmetric Numeral Systems) lossless and near-lossless image compressor, which is based on JPEG-LS standard. The design is implemented in two FPGA generations, evaluating its performance for different codec configurations. The tests show that the design is capable of up to 40.5 MPixels/s and 124 MPixels/s per lane for Zynq 7020 and UltraScale+ FPGAs, respectively. Compared to the single thread LOCO-ANS software implementation running in a 1.2 GHz Raspberry Pi 3B, each hardware lane achieves 6.5 times higher throughput, even when implemented in an older and cost-optimized chip like the Zynq 7020. Results are also presented for a lossless only version, which achieves a lower footprint and approximately 50% higher performance than the version that supports both lossless and near-lossless. Interestingly, these great results were obtained applying High-Level Synthesis, describing the coder with C++ code, which tends to establish a trade-off between design time and quality of results. These results show that the algorithm is very suitable for hardware implementation. Moreover, the implemented system is faster and achieves higher compression than the best previously available near-lossless JPEG-LS hardware implementation.