2008 Asia and South Pacific Design Automation Conference
Latest Publications

TOTAL DOCUMENTS

157

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

9781424419210, 9781424419227

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Multithreaded coprocessor interface for multi-core multimedia SoC

2008 Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.2008.4483922 ◽

2008 ◽

Author(s):

Shih-Hao Ou ◽

Tay-Jyi Lin ◽

Xiang Sheng Deng ◽

Zhi Hong Zhuo ◽

Chih Wei Liu

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Efficient techniques for 3-D impedance extraction using mixed boundary element method

2008 Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.2008.4483931 ◽

2008 ◽

Cited By ~ 1

Author(s):

Fang Gong ◽

Wenjian Yu ◽

Zeyi Wang ◽

Zhiping Yu ◽

Changhao Yan

Keyword(s):

Boundary Element Method ◽

Boundary Element ◽

Mixed Boundary ◽

Impedance Extraction ◽

Element Method

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Reliability-aware design for nanometer-scale devices

2008 Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.2008.4484011 ◽

2008 ◽

Cited By ~ 12

Author(s):

David Atienza ◽

Giovanni De Micheli ◽

Luca Benini ◽

Jose L. Ayala ◽

Pablo G. Del Valle ◽

...

Keyword(s):

Nanometer Scale

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DPlace2.0: A stable and efficient analytical placement based on diffusion

2008 Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.2008.4483972 ◽

2008 ◽

Cited By ~ 2

Author(s):

Tao Luo ◽

David Z. Pan

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NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?

2008 Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.2008.4484047 ◽

2008 ◽

Cited By ~ 30

Author(s):

Kunhyuk Kang ◽

Saakshi Gangwal ◽

Sang Phill Park ◽

Roy Kaushik

Keyword(s):

Performance Degradation ◽

Memory Circuits

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Automatic interface synthesis based on the classification of interface protocols of IPs

2008 Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.2008.4484020 ◽

2008 ◽

Author(s):

ChangRyul Yun ◽

DongSoo Kang ◽

YoungHwan Bae ◽

Hanhn Cho ◽

KyoungSon Jhang

Keyword(s):

Interface Synthesis

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Reconfigurable RTD-based circuit elements of complete logic functionality

2008 Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.2008.4484045 ◽

2008 ◽

Author(s):

Yexin Zheng ◽

Chao Huang

Keyword(s):

Circuit Elements

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Global optimization of common subexpressions for multiplierless synthesis of multiple constant multiplications

2008 Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.2008.4483924 ◽

2008 ◽

Cited By ~ 4

Author(s):

Yuen-Hong Alvin Ho ◽

Chi-Un Lei ◽

Hing-Kit Kwan ◽

Ngai Wong

Keyword(s):

Global Optimization ◽

Common Subexpressions

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Variability-driven module selection with joint design time optimization and post-silicon tuning

2008 Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.2008.4483963 ◽

2008 ◽

Cited By ~ 15

Author(s):

Feng Wang ◽

Xiaoxia Wu ◽

Yuan Xie

Keyword(s):

Joint Design ◽

Design Time ◽

Time Optimization ◽

Module Selection

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A 1.2GHz delayed clock generator for high-speed microprocessors

2008 Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.2008.4484068 ◽

2008 ◽

Author(s):

Inhwa Jung ◽

Moo-Young Kim ◽

Chulwoo Kim

Keyword(s):

High Speed ◽

Clock Generator

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2008 Asia and South Pacific Design Automation ConferenceLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Multithreaded coprocessor interface for multi-core multimedia SoC

Efficient techniques for 3-D impedance extraction using mixed boundary element method

Reliability-aware design for nanometer-scale devices

DPlace2.0: A stable and efficient analytical placement based on diffusion

NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?

Automatic interface synthesis based on the classification of interface protocols of IPs

Reconfigurable RTD-based circuit elements of complete logic functionality

Global optimization of common subexpressions for multiplierless synthesis of multiple constant multiplications

Variability-driven module selection with joint design time optimization and post-silicon tuning

A 1.2GHz delayed clock generator for high-speed microprocessors

2008 Asia and South Pacific Design Automation Conference
Latest Publications