2007 IEEE International Symposium on Nanoscale Architectures
Latest Publications

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Published By IEEE

9781424417902, 9781424417919

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Crossbar latch-based combinational and sequential logic for nano FPGA

2007 IEEE International Symposium on Nanoscale Architectures ◽

10.1109/nanoarch.2007.4400866 ◽

2007 ◽

Author(s):

T. Mohamed ◽

G. A. Jullien ◽

W. Badawy

Keyword(s):

Sequential Logic

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Robust self-assembly of interconnects by parallel DNA growth

2007 IEEE International Symposium on Nanoscale Architectures ◽

10.1109/nanoarch.2007.4400860 ◽

2007 ◽

Cited By ~ 2

Author(s):

Masoud Hashempour ◽

Zahra Mashreghian Arani ◽

Fabrizio Lombardi

Keyword(s):

Self Assembly

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A ballistic nanoelectronic device simulator

2007 IEEE International Symposium on Nanoscale Architectures ◽

10.1109/nanoarch.2007.4400856 ◽

2007 ◽

Author(s):

Dennis Huo ◽

Qiaoyan Yu ◽

Paul Ampadu

Keyword(s):

Nanoelectronic Device

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Prospects for the development of digital CMOL circuits

2007 IEEE International Symposium on Nanoscale Architectures ◽

10.1109/nanoarch.2007.4400865 ◽

2007 ◽

Cited By ~ 10

Author(s):

Dmitri B. Strukov ◽

Konstantin K. Likharev

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Improving nanoelectronic designs using a statistical approach to identify key parameters in circuit level SEU simulations

2007 IEEE International Symposium on Nanoscale Architectures ◽

10.1109/nanoarch.2007.4400857 ◽

2007 ◽

Cited By ~ 3

Author(s):

Drew C. Ness ◽

Christian J. Hescott ◽

David J. Lilja

Keyword(s):

Statistical Approach

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Analysis of defect tolerance in molecular electronics using information-theoretic measures

2007 IEEE International Symposium on Nanoscale Architectures ◽

10.1109/nanoarch.2007.4400853 ◽

2007 ◽

Author(s):

Jianwei Dai ◽

Lei Wang ◽

Faquir Jain

Keyword(s):

Molecular Electronics ◽

Defect Tolerance ◽

Information Theoretic ◽

Information Theoretic Measures

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A fast, numerical circuit-level model of carbon nanotube transistor

2007 IEEE International Symposium on Nanoscale Architectures ◽

10.1109/nanoarch.2007.4400855 ◽

2007 ◽

Cited By ~ 6

Author(s):

Tom J. Kazmierski ◽

Dafeng Zhou ◽

Bashir M. Al-Hashimi

Keyword(s):

Carbon Nanotube ◽

Level Model

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Design-space exploration of fault-tolerant building blocks for large-scale quantum computing

2007 IEEE International Symposium on Nanoscale Architectures ◽

10.1109/nanoarch.2007.4400851 ◽

2007 ◽

Author(s):

Tzvetan S. Metodi ◽

Andrew W. Cross ◽

Darshan D. Thaker ◽

Isaac L. Chuang ◽

Frederic T. Chong

Keyword(s):

Quantum Computing ◽

Large Scale ◽

Design Space Exploration ◽

Design Space ◽

Fault Tolerant ◽

Space Exploration ◽

Building Blocks

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Clocking nanocircuits for nanocomputers and other nanoelectronic systems

2007 IEEE International Symposium on Nanoscale Architectures ◽

10.1109/nanoarch.2007.4400867 ◽

2007 ◽

Author(s):

Shamik Das ◽

Matthew F. Bauwens

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A pageable, defect-tolerant nanoscale memory system

2007 IEEE International Symposium on Nanoscale Architectures ◽

10.1109/nanoarch.2007.4400862 ◽

2007 ◽

Cited By ~ 7

Author(s):

Susmit Biswas ◽

Frederic T. Chong ◽

Tzvetan S. Metodi ◽

Ryan Kastner

Keyword(s):

Memory System

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2007 IEEE International Symposium on Nanoscale ArchitecturesLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Crossbar latch-based combinational and sequential logic for nano FPGA

Robust self-assembly of interconnects by parallel DNA growth

A ballistic nanoelectronic device simulator

Prospects for the development of digital CMOL circuits

Improving nanoelectronic designs using a statistical approach to identify key parameters in circuit level SEU simulations

Analysis of defect tolerance in molecular electronics using information-theoretic measures

A fast, numerical circuit-level model of carbon nanotube transistor

Design-space exploration of fault-tolerant building blocks for large-scale quantum computing

Clocking nanocircuits for nanocomputers and other nanoelectronic systems

A pageable, defect-tolerant nanoscale memory system

2007 IEEE International Symposium on Nanoscale Architectures
Latest Publications