[Proceedings] EURO ASIC `90
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90

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4

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Published By IEEE Comput. Soc

0818620668

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

A methodology for performance driven data-path compilation

[Proceedings] EURO ASIC `90 ◽

10.1109/easic.1990.207925 ◽

2002 ◽

Cited By ~ 4

Author(s):

S. Note ◽

F. Catthoor ◽

G. Goossens ◽

H. De Man

Keyword(s):

Data Path

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Thin film transistors modeling and parameters extraction tool

[Proceedings] EURO ASIC `90 ◽

10.1109/easic.1990.207984 ◽

2002 ◽

Author(s):

O. Declerck ◽

J.P. Bardyn

Keyword(s):

Thin Film ◽

Thin Film Transistors ◽

Parameters Extraction

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Built-in self-test for generated blocks in an ASIC environment

[Proceedings] EURO ASIC `90 ◽

10.1109/easic.1990.207962 ◽

2002 ◽

Cited By ~ 1

Author(s):

V. Bruchner ◽

A. Achuetz

Keyword(s):

Self Test ◽

Built In Self Test

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Silicon-bipolar ASICs for 2.5 Gbit/s systems-designed and implemented both as full custom circuits and as personalized transistor arrays

[Proceedings] EURO ASIC `90 ◽

10.1109/easic.1990.207918 ◽

2002 ◽

Author(s):

W. Bambach ◽

R.H. Derksen ◽

V. Luck ◽

M. Salvasohn ◽

H. Wernz

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PLAYL: a general-purpose data path assembler

[Proceedings] EURO ASIC `90 ◽

10.1109/easic.1990.207951 ◽

2002 ◽

Author(s):

N.H. Nam ◽

D. Laurent

Keyword(s):

General Purpose ◽

Data Path

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Design of an integrated programmable neurostimulator

[Proceedings] EURO ASIC `90 ◽

10.1109/easic.1990.207917 ◽

2002 ◽

Author(s):

A. Kachouri ◽

M. Robert ◽

D. Deschacht ◽

N. Lakhoua ◽

D. Auvergne

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An ASIC controller for the TMS 320, 2-generation digital signal processor

[Proceedings] EURO ASIC `90 ◽

10.1109/easic.1990.207939 ◽

2002 ◽

Author(s):

G. Creanza ◽

O. Ventrella ◽

G. Colangeli ◽

E. Subiaco

Keyword(s):

Digital Signal Processor ◽

Digital Signal ◽

Signal Processor

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KIM 20: a symbolic RISC microprocessor for embedded advanced control

[Proceedings] EURO ASIC `90 ◽

10.1109/easic.1990.207929 ◽

2002 ◽

Author(s):

J.-C. Heudin

Keyword(s):

Advanced Control

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High-level synthesis and optimization strategies in Hercules and Hebe

[Proceedings] EURO ASIC `90 ◽

10.1109/easic.1990.207906 ◽

2002 ◽

Cited By ~ 9

Author(s):

D. Ku ◽

G. De Micheli

Keyword(s):

High Level Synthesis ◽

High Level

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Comparison between a chip for realtime skeleting of images and its corresponding discrete realisation-a case study

[Proceedings] EURO ASIC `90 ◽

10.1109/easic.1990.207973 ◽

2002 ◽

Cited By ~ 2

Author(s):

A.J. Maeder ◽

R.H. Rauscher

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