digital signal processor
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Micromachines ◽  
2021 ◽  
Vol 12 (12) ◽  
pp. 1587
Chao-Tsung Ma ◽  
Zhen-Yu Tsai ◽  
Hung-Hsien Ku ◽  
Chin-Lung Hsieh

In order to efficiently facilitate various research works related to power converter design and testing for solar photovoltaic (PV) generation systems, it is a great merit to use advanced power-converter-based and digitally controlled PV emulators in place of actual PV modules to reduce the space, cost, and time to obtain the required scenarios of solar irradiances for various functional tests. This paper presents a flexible PV emulator based on gallium nitride (GaN), a wide-bandgap (WBG) semiconductor, and a based synchronous buck converter and controlled with a digital signal processor (DSP). With the help of GaN-based switching devices, the proposed emulator can accurately mimic the dynamic voltage-current characteristics of any PV module under normal irradiance and partial shading conditions. With the proposed PV emulator, it is possible to closely emulate any PV module characteristic both theoretically, based on manufacturer’s datasheets, and experimentally, based on measured data from practical PV modules. A curve fitting algorithm is used to handle the real-time generation of control signals for the digital controller. Both simulation with computer software and implementation on 1 kW GaN-based experimental hardware using Texas Instruments DSP as the controller have been carried out. Results show that the proposed emulator achieves efficiency as high as 99.05% and exhibits multifaceted application features in tracking various PV voltage and current parameters, demonstrating the feasibility and excellent performance of the proposed PV emulator.

Energies ◽  
2021 ◽  
Vol 14 (23) ◽  
pp. 8073
Tian-Hua Liu ◽  
Kai-Hsiang Chang ◽  
Jia-Han Li

The matrix converter-based IPMSM drive has 360 Hz virtual DC-bus voltage variations which produce severe stator harmonic currents. To solve this problem, a speed-loop classical periodic controller and two current-loop periodic controllers, including a classical periodic controller and a selective harmonic controller, are proposed in this paper. By using the proposed methods, the harmonic currents are obviously reduced and the speed responses of the IPMSM are clearly improved. A detailed analysis is discussed. A digital signal processor, type SH7237, manufactured by Renesas Electronics Corporation is used for the control algorithms. Experimental results show that those proposed periodic controllers reduce up to nearly 32% of the total harmonic distortion at the stator currents, and also apparently improve the transient, tracking, and repetitive load disturbance speed responses.

Abidaoun H. Shallal ◽  
Assaad F. Nashee ◽  
Aws Ezzaldeen Abbas

In the industrial application, the induction motors (IMs) and the digital signal processing (ZQ28335) combination are very important in the scientific field. Two thirds of consumption of electricity is due to motor driven equipment. The direct torque control (DTC) is the standard of the industry and it has fast response control system applications. The drawback of DTC is the flux and torque ripples in the measurements. The scalar control can be considered as a solution to this drawback but with poor response. Torque and speed of IM are controlling individually, the variable speed drive (VSDs) is used. This occurs with variation of the voltage and frequency of IM supply. To decrease the levels of flux and torque ripples, 3-level inverters represent an attractive technique. The compromise of a huge flux and torque at the beginning level and low values at steady state of operation is crucial to ensure better stability with feedback linearization of the nonlinear behavior. In this paper, VSD with DTC IM with multilevel inverter with the newest version of ZQ28335 digital signal processor (DSP) is proposed. Emulation and the results of experiment through DSP ZQ28335 make certain correct dynamic response to the operations of torque and flux.

2021 ◽  
Vol 6 (4) ◽  
pp. 320-331
Yukun Luo ◽  

Field-programmable gate array (FPGA) is a powerful platform that can play an essential role in high-performance digital control of power electronics systems. However, the FPGA system’s design is quite different from that of a traditional microprocessor or a digital signal processor (DSP). Instead of sequential programming using high-level languages, such as C/C++, FPGA controller implementation requires a hardware description language (HDL) such as Verilog and VHDL, which requires extensive verification and optimization during the design process. This paper proposes a systematic FPGA design methodology with optimum resource utilization for rapid prototyping of high-performance power electronics applications to facilitate the widespread adoption of FPGA technology in power electronics. The FPGA controller design is concurrent with the power stage and utilizes high-level synthesis (HLS) tools and Simulink code generation toolbox. This paper covers the detailed design, implementation, and experimental validation of two specific applications, i.e., an active power filter (APF) and a motor emulator (ME), demonstrating the generalized features of the methodology. Employing fundamentally different control structures, both application examples achieve ultra-high current control bandwidth leveraging SiC MOSFETs switching at no less than 100 kHz.

Redouane Es-sadaoui ◽  
Jamal Khallaayoune ◽  
Tamara Brizard

<p>The attenuation of global positioning system (GPS) in water medium makes localization of autonomous uderwater vehicles (AUVs) particularly challenging. The long baseline (LBL) positioning system can extend GPS using beacons as references. This work aims at building an acoustic LBL-based system able to localize AUVs operating in swarms thanks to a small size acoustic transceiver embedded onboard AUVs and implementing range-based localization algorithms to estimate the swarm coordinates in real-time. The distances computation between navigating AUVs and fixed beacons were implemented in a digital signal processor (DSP) which computes the time-of-arrival (ToA) of incoming pure tone acoustic waves. The principle of design, hardware architecture, implementation, simulations and sea experiments are described in this paper. The experimental data showed an average deviation around 0.62 m when an AUV is placed at 45 m far away from a beacon. This deviation increases with distance: around 4.8 m measured at 500 m. This performance can be improved by taking into consideration the two main factors examined in this paper, which are sound velocity profile and propagation model.</p>

Processes ◽  
2021 ◽  
Vol 9 (12) ◽  
pp. 2132
En-Chih Chang ◽  
Hung-Liang Cheng ◽  
Chien-Hsuan Chang ◽  
Rong-Ching Wu ◽  
Hong-Wei Xu ◽  

This paper puts forward an optimal quick-response variable structure control with a single-phase sine-wave inverter application, which keeps harmonic distortion as low as possible under various conditions of loading. Our proposed solution gives an improvement in architecture in which a quick-response variable structure control (QRVSC) is combined with a brain storm optimization (BSO) algorithm. Notwithstanding the intrinsic resilience of a typical VSC with respect to changes in plant parameters and loading disruptions, the system state convergence towards zero normally proceeds at an infinitely long-time asymptotically, and chattering behavior frequently takes place. The QRVSC for ensuring speedy limited-time convergence with the system state to the balancing point is devised, whilst the BSO will be employed to appropriately regulate the parametric gains in the QRVSC for the elimination of chattering phenomena. From the mix of both a QRVSC together with a BSO, a low total harmonic distortion (THD) as well as a high dynamic response across different types of loading is generated by a closed-loop inverter. The proposed solution is implemented on a practicable single-phase sine-wave inverter under the control of a TI DSP (Texas Instruments Digital Signal Processor). It has experimentally shown the simulation findings as well as the mathematical theoretical analysis, displaying that both quick transient reaction as well as stable performance could be obtained. The proposed solution successfully inhibits voltage harmonics in compliance with IEEE 519-2014’s stringent standard of limiting THD values to less than 5%.

Usthulamuri Penchalaiah ◽  
V. G. Siva Kumar

Digital Signal Processors (DSP) have a ubiquitous presence in almost all civil and military signal processing applications, including mission critical environments like nuclear reactors, process control etc. Arithmetic and Logic units (ALU), being the heart of any digital signal processor, play critical and decisive roles in achieving the required parameter benchmarks and the overall efficiency and robustness of the digital signal processor. State of the art research has shown successful traction with the performance requirements of critical Multiply-Accumulate (MAC) parameters, like reduced power consumption, small electronic real estate footprint and reduction in delay with the associated design complexity. Judicious placement of its building blocks, namely, the truncated multiplier and half-sum carry generation-sum carry generation (HSCG-SCG) adder in the architectural design of ALU and the type of adder and multiplier circuits selected are the core decisions that decide the overall performance of the ALU. To overcome the drawback and to improve the performance further, this work proposes a new architecture for the square root (SQRT) carry select adder (CSLA) using half-sum generation (HSG), half-carry generation (HCG), full-sum generation (FSG) and full-carry generation (FCG) blocks. The proposed design contains N-bit architecture, and comparative results are considered for 8-bit, 16-bit and 32-bit combinations. All the designs are implemented in the Xilinx ISE environment and the results show that better area, power, and delay performance compared to the state of art methods.

2021 ◽  
Stefan A. Damjancevic ◽  
Samuel Ajay Dasgupta ◽  
Emil Matus ◽  
Dmitry Utyanksy ◽  
Pieter van der Wolf ◽  

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