Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05)

2006 ◽

Cited By ~ 2

Author(s):

T. Hironaka ◽

M. Maeda ◽

K. Tanigawa ◽

T. Sueyoshi ◽

K. Aoyama ◽

...

Keyword(s):

Register File ◽

Superscalar Processor

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Continuum Computer Architecture for Nano-Scale and Ultra-High Clock Rate Technologies

Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05) ◽

10.1109/iwia.2005.27 ◽

2006 ◽

Cited By ~ 1

Author(s):

T. Sterling ◽

M. Brodowicz

Keyword(s):

Computer Architecture ◽

Clock Rate ◽

Nano Scale

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On the Use of Bit Filters in Shared Nothing Partitioned Systems

Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05) ◽

10.1109/iwia.2005.34 ◽

2006 ◽

Author(s):

J. Aguilar-Saborit ◽

V. Muntes-Mulero ◽

C. Zuzarte ◽

H. Pereyra ◽

Josep-L. Larriba-Pey

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The Bimode++ Branch Predictor

Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05) ◽

10.1109/iwia.2005.43 ◽

2006 ◽

Author(s):

K. Kise ◽

T. Katagiri ◽

H. Honda ◽

T. Yuba

Keyword(s):

Branch Predictor

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An Exploration of the Technology Space for Multi-Core Memory/Logic Chips for Highly Scalable Parallel Systems

Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05) ◽

10.1109/iwia.2005.24 ◽

2006 ◽

Cited By ~ 9

Author(s):

P.M. Kogge

Keyword(s):

Parallel Systems ◽

Core Memory

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Optimal Loop-Unrolling Mechanisms and Architectural Extensions for an Energy-Efficient Design of Shared Register Files in MPSoCs

Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05) ◽

10.1109/iwia.2005.35 ◽

2006 ◽

Cited By ~ 2

Author(s):

J.L. Ayala ◽

D. Atienza ◽

M. Lopez-Vallejo ◽

J.M. Mendias ◽

R. Hermida ◽

...

Keyword(s):

Energy Efficient ◽

Efficient Design ◽

Loop Unrolling ◽

Register Files ◽

Energy Efficient Design

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A New Kind of Processor Interface for a System-on-Chip Processor with TIE Ports and TIE Queues of Xtensa LX

Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05) ◽

10.1109/iwia.2005.23 ◽

2006 ◽

Cited By ~ 1

Author(s):

T. Tohara

Keyword(s):

System On Chip ◽

On Chip

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Incorporating a Secure Coprocessor in the Database-as-a-Service Model

Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05) ◽

10.1109/iwia.2005.28 ◽

2006 ◽

Cited By ~ 9

Author(s):

E. Mykletun ◽

G. Tsudik

Keyword(s):

Service Model ◽

Database As A Service

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Preliminary Evaluation of a FPGA-Based-Prototype of DIMMnet-2 Network Interface

Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05) ◽

10.1109/iwia.2005.38 ◽

2006 ◽

Cited By ~ 4

Author(s):

N. Tanabe ◽

A. Kitamura ◽

T. Miyashiro ◽

Y. Miyabe ◽

T. Izawa ◽

...

Keyword(s):

Network Interface ◽

Preliminary Evaluation

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PRESTOR-1: A Processor Extending Multithreaded Architecture

Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05) ◽

10.1109/iwia.2005.39 ◽

2006 ◽

Cited By ~ 3

Author(s):

K. Tanaka

Keyword(s):

Multithreaded Architecture

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Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05)
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Superscalar Processor with Multi-Bank Register File

Continuum Computer Architecture for Nano-Scale and Ultra-High Clock Rate Technologies

On the Use of Bit Filters in Shared Nothing Partitioned Systems

The Bimode++ Branch Predictor

An Exploration of the Technology Space for Multi-Core Memory/Logic Chips for Highly Scalable Parallel Systems

Optimal Loop-Unrolling Mechanisms and Architectural Extensions for an Energy-Efficient Design of Shared Register Files in MPSoCs

A New Kind of Processor Interface for a System-on-Chip Processor with TIE Ports and TIE Queues of Xtensa LX

Incorporating a Secure Coprocessor in the Database-as-a-Service Model

Preliminary Evaluation of a FPGA-Based-Prototype of DIMMnet-2 Network Interface

PRESTOR-1: A Processor Extending Multithreaded Architecture

Export Citation Format

Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Superscalar Processor with Multi-Bank Register File

Continuum Computer Architecture for Nano-Scale and Ultra-High Clock Rate Technologies

On the Use of Bit Filters in Shared Nothing Partitioned Systems

The Bimode++ Branch Predictor

An Exploration of the Technology Space for Multi-Core Memory/Logic Chips for Highly Scalable Parallel Systems

Optimal Loop-Unrolling Mechanisms and Architectural Extensions for an Energy-Efficient Design of Shared Register Files in MPSoCs

A New Kind of Processor Interface for a System-on-Chip Processor with TIE Ports and TIE Queues of Xtensa LX

Incorporating a Secure Coprocessor in the Database-as-a-Service Model

Preliminary Evaluation of a FPGA-Based-Prototype of DIMMnet-2 Network Interface

PRESTOR-1: A Processor Extending Multithreaded Architecture

Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05)
Latest Publications