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1990 Proceedings. International Conference on Wafer Scale Integration
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TOTAL DOCUMENTS
43
(FIVE YEARS 0)
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6
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Published By IEEE Comput. Soc. Press
0818690135
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Testing wafer scale arrays: constant testability under multiple faults
1990 Proceedings. International Conference on Wafer Scale Integration
◽
10.1109/icwsi.1990.63908
◽
2002
◽
Author(s):
D. Sciuto
◽
F. Lombardi
Keyword(s):
Multiple Faults
◽
Wafer Scale
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A general configurable architecture for WSI implementation for neural nets
1990 Proceedings. International Conference on Wafer Scale Integration
◽
10.1109/icwsi.1990.63891
◽
2002
◽
Cited By ~ 4
Author(s):
F. Distante
◽
M.G. Sami
◽
G. Storti Gajani
Keyword(s):
Neural Nets
◽
Configurable Architecture
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Defect tolerant implementations of feed-forward and recurrent neural networks
1990 Proceedings. International Conference on Wafer Scale Integration
◽
10.1109/icwsi.1990.63897
◽
2002
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Cited By ~ 1
Author(s):
P. Franzon
◽
D. van den Bout
◽
J. Paulos
◽
T. Miller
◽
W. Snyder
◽
...
Keyword(s):
Neural Networks
◽
Recurrent Neural Networks
◽
Feed Forward
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Hybrid wafer scale interconnection inventing a new technology
1990 Proceedings. International Conference on Wafer Scale Integration
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10.1109/icwsi.1990.63914
◽
2002
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Author(s):
R. Schmidt
Keyword(s):
New Technology
◽
Wafer Scale
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A linear-array WSI architecture for improved yield and performance
1990 Proceedings. International Conference on Wafer Scale Integration
◽
10.1109/icwsi.1990.63887
◽
2002
◽
Cited By ~ 6
Author(s):
R.W. Horst
Keyword(s):
Linear Array
◽
And Performance
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The Lincoln programmable image-processing wafer
1990 Proceedings. International Conference on Wafer Scale Integration
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10.1109/icwsi.1990.63878
◽
2002
◽
Cited By ~ 6
Author(s):
R. Berger
◽
A. Bertapelli
◽
R. Frankel
◽
J.J. Hunt
◽
J. Mann
◽
...
Keyword(s):
Image Processing
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Divide-and-conquer in wafer scale array testing
1990 Proceedings. International Conference on Wafer Scale Integration
◽
10.1109/icwsi.1990.63910
◽
2002
◽
Cited By ~ 1
Author(s):
Y.-H. Choi
◽
T. Jung
Keyword(s):
Divide And Conquer
◽
Wafer Scale
◽
Array Testing
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Defect tolerant sorting networks for WSI implementation
1990 Proceedings. International Conference on Wafer Scale Integration
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10.1109/icwsi.1990.63893
◽
2002
◽
Cited By ~ 3
Author(s):
Sheng-Chiech Liang
◽
Sy-Yen Kuo
Keyword(s):
Sorting Networks
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Implementation of configurable hardware using wafer scale integration
1990 Proceedings. International Conference on Wafer Scale Integration
◽
10.1109/icwsi.1990.63885
◽
2002
◽
Cited By ~ 1
Author(s):
T. Kean
◽
J. Gray
◽
B. Pruniaux
Keyword(s):
Wafer Scale
◽
Wafer Scale Integration
◽
Configurable Hardware
◽
Scale Integration
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A 64 Mb MROM with good pair selection architecture
1990 Proceedings. International Conference on Wafer Scale Integration
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10.1109/icwsi.1990.63883
◽
2002
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Author(s):
K. Nakahara
◽
H. Hatanaka
◽
S. Kura
◽
Y. Suminaga
◽
Y. Hotta
◽
...
Keyword(s):
Good Pair
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