Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors
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TOTAL DOCUMENTS

117

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Published By IEEE Comput. Soc. Press

0818665653

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Optimal design of self-damped lossy transmission lines for multichip modules

Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors ◽

10.1109/iccd.1994.331984 ◽

2002 ◽

Cited By ~ 10

Author(s):

J.S.-H. Wang ◽

W.W.-M. Dai

Keyword(s):

Optimal Design ◽

Transmission Lines ◽

Multichip Modules ◽

Lossy Transmission

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A massively parallel multithreaded architecture: DAVRID

Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors ◽

10.1109/iccd.1994.331857 ◽

2002 ◽

Author(s):

Sangho Ha ◽

Junghwan Kim ◽

Eunha Rho ◽

Yoonhee Nah ◽

Sangyong Han ◽

...

Keyword(s):

Massively Parallel ◽

Multithreaded Architecture

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Differential routing of MCMs-CIF: the ideal bifurcation medium

Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors ◽

10.1109/iccd.1994.331985 ◽

2002 ◽

Cited By ~ 4

Author(s):

J. Loy ◽

A. Garg ◽

M. Krishnamoorthy ◽

J. McDonald

Keyword(s):

The Ideal

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A new asynchronous multiplier using Enable/Disable CMOS Differential Logic

Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors ◽

10.1109/iccd.1994.331911 ◽

2002 ◽

Cited By ~ 1

Author(s):

E. de Angel ◽

E. Swartzlander ◽

J. Abraham

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Timing verification and optimization for the PowerPC processor family

Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors ◽

10.1109/iccd.1994.331929 ◽

2002 ◽

Cited By ~ 6

Author(s):

R.E. Mains ◽

T.A. Mosher ◽

L.P.P.P. van Ginneken ◽

R.F. Damiano

Keyword(s):

Timing Verification

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Multifault testable circuits based on binary parity diagrams

Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors ◽

10.1109/iccd.1994.331927 ◽

2002 ◽

Author(s):

S. Kundu

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Design of TSC code-disjoint inverter-free PLA's for separable unordered codes

Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors ◽

10.1109/iccd.1994.331871 ◽

2002 ◽

Cited By ~ 3

Author(s):

S.J. Piestrak

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Microarchitectural synthesis of performance-constrained, low-power VLSI designs

Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors ◽

10.1109/iccd.1994.331916 ◽

2002 ◽

Cited By ~ 27

Author(s):

L. Goodby ◽

A. Orailoglu ◽

P.M. Chau

Keyword(s):

Low Power

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Continuations in hardware-software codesign

Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors ◽

10.1109/iccd.1994.331902 ◽

2002 ◽

Cited By ~ 1

Author(s):

M.E. Tuna ◽

S.D. Johnson ◽

R.G. Burger

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Grammar-based optimization of synthesis scenarios

Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors ◽

10.1109/iccd.1994.331846 ◽

2002 ◽

Cited By ~ 2

Author(s):

A. Kuehlmann ◽

L.P.P.P. Van Ginneken

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Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and ProcessorsLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc. Press

Optimal design of self-damped lossy transmission lines for multichip modules

A massively parallel multithreaded architecture: DAVRID

Differential routing of MCMs-CIF: the ideal bifurcation medium

A new asynchronous multiplier using Enable/Disable CMOS Differential Logic

Timing verification and optimization for the PowerPC processor family

Multifault testable circuits based on binary parity diagrams

Design of TSC code-disjoint inverter-free PLA's for separable unordered codes

Microarchitectural synthesis of performance-constrained, low-power VLSI designs

Continuations in hardware-software codesign

Grammar-based optimization of synthesis scenarios

Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors
Latest Publications