2014 IEEE 44th International Symposium on Multiple-Valued Logic
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(FIVE YEARS 0)

Published By IEEE

9781479935352

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2014 IEEE 44th International Symposium on Multiple-Valued Logic ◽

10.1109/ismvl.2014.8 ◽

2014 ◽

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Maximal and Minimal Closed Classes in Multiple-Valued Logic

2014 IEEE 44th International Symposium on Multiple-Valued Logic ◽

10.1109/ismvl.2014.18 ◽

2014 ◽

Author(s):

Tamas Waldhauser

Keyword(s):

Multiple Valued Logic

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First-Order Logic Based on Set Approximation: A Partial Three-Valued Approach

2014 IEEE 44th International Symposium on Multiple-Valued Logic ◽

10.1109/ismvl.2014.31 ◽

2014 ◽

Cited By ~ 1

Author(s):

Tamas Mihalydeak

Keyword(s):

Order Logic ◽

First Order Logic ◽

First Order ◽

Set Approximation

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On Submodular and Supermodular Functions on Lattices and Related Structures

2014 IEEE 44th International Symposium on Multiple-Valued Logic ◽

10.1109/ismvl.2014.43 ◽

2014 ◽

Author(s):

Dan A. Simovici

Keyword(s):

Supermodular Functions

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Soft-Delay-Error Evaluation in Content-Addressable Memory

2014 IEEE 44th International Symposium on Multiple-Valued Logic ◽

10.1109/ismvl.2014.46 ◽

2014 ◽

Author(s):

Naoya Onizawa ◽

Shoun Matsunaga ◽

Noboru Sakimura ◽

Ryusuke Nebashi ◽

Tadahiko Sugibayashi ◽

...

Keyword(s):

Error Evaluation ◽

Content Addressable Memory

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Copyright Page

2014 IEEE 44th International Symposium on Multiple-Valued Logic ◽

10.1109/ismvl.2014.3 ◽

2014 ◽

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An Algorithm for Constructing a Minimal Register with Non-linear Update Generating a Given Sequence

2014 IEEE 44th International Symposium on Multiple-Valued Logic ◽

10.1109/ismvl.2014.52 ◽

2014 ◽

Cited By ~ 4

Author(s):

Nan Li ◽

Elena Dubrova

Keyword(s):

Non Linear

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An Update Method for a CAM Emulator Using an LUT Cascade Based on an EVMDD (K)

2014 IEEE 44th International Symposium on Multiple-Valued Logic ◽

10.1109/ismvl.2014.9 ◽

2014 ◽

Cited By ~ 3

Author(s):

Hiroki Nakahara ◽

Tsutomu Sasao ◽

Munehiro Matsuura

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Title Page iii

2014 IEEE 44th International Symposium on Multiple-Valued Logic ◽

10.1109/ismvl.2014.2 ◽

2014 ◽

Keyword(s):

Title Page

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Efficient Reversible Logic Synthesis via Isomorphic Subgraph Matching

2014 IEEE 44th International Symposium on Multiple-Valued Logic ◽

10.1109/ismvl.2014.26 ◽

2014 ◽

Cited By ~ 5

Author(s):

Mridul Krishna ◽

Anupam Chattopadhyay

Keyword(s):

Logic Synthesis ◽

Reversible Logic ◽

Subgraph Matching ◽

Reversible Logic Synthesis

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2014 IEEE 44th International Symposium on Multiple-Valued LogicLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Additional Reviewers

Maximal and Minimal Closed Classes in Multiple-Valued Logic

First-Order Logic Based on Set Approximation: A Partial Three-Valued Approach

On Submodular and Supermodular Functions on Lattices and Related Structures

Soft-Delay-Error Evaluation in Content-Addressable Memory

Copyright Page

An Algorithm for Constructing a Minimal Register with Non-linear Update Generating a Given Sequence

An Update Method for a CAM Emulator Using an LUT Cascade Based on an EVMDD (K)

Title Page iii

Efficient Reversible Logic Synthesis via Isomorphic Subgraph Matching

2014 IEEE 44th International Symposium on Multiple-Valued Logic
Latest Publications