[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture
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Published By IEEE Comput. Soc. Press

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Maximizing performance in a striped disk array

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture ◽

10.1109/isca.1990.134542 ◽

2002 ◽

Cited By ~ 63

Author(s):

P.M. Chen ◽

D.A. Patterson

Keyword(s):

Disk Array

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Adaptive software cache management for distributed shared memory architectures

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture ◽

10.1109/isca.1990.134515 ◽

2002 ◽

Cited By ~ 37

Author(s):

J.K. Bennett ◽

J.B. Carter ◽

W. Zwaenepoel

Keyword(s):

Shared Memory ◽

Distributed Shared Memory ◽

Cache Management ◽

Adaptive Software ◽

Memory Architectures ◽

Shared Memory Architectures ◽

Software Cache

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The TLB slice-a low-cost high-speed address translation mechanism

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture ◽

10.1109/isca.1990.134546 ◽

2002 ◽

Cited By ~ 22

Author(s):

G. Taylor ◽

P. Davies ◽

M. Farmwald

Keyword(s):

High Speed ◽

Low Cost ◽

Address Translation ◽

Translation Mechanism

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Boosting beyond static scheduling in a superscalar processor

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture ◽

10.1109/isca.1990.134545 ◽

2002 ◽

Cited By ~ 30

Author(s):

M.D. Smith ◽

M.S. Lam ◽

M.A. Horowitz

Keyword(s):

Superscalar Processor ◽

Static Scheduling

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The directory-based cache coherence protocol for the DASH multiprocessor

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture ◽

10.1109/isca.1990.134520 ◽

2002 ◽

Cited By ~ 181

Author(s):

D. Lenoski ◽

J. Laudon ◽

K. Gharachorloo ◽

A. Gupta ◽

J. Hennessy

Keyword(s):

Cache Coherence ◽

Cache Coherence Protocol

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PLUS: a distributed shared-memory system

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture ◽

10.1109/isca.1990.134514 ◽

2002 ◽

Cited By ~ 27

Author(s):

R. Bisiani ◽

M. Ravishankar

Keyword(s):

Shared Memory ◽

Distributed Shared Memory ◽

Memory System ◽

Shared Memory System

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Monsoon: an explicit token-store architecture

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture ◽

10.1109/isca.1990.134511 ◽

2002 ◽

Cited By ~ 88

Author(s):

G.M. Papadopoulos ◽

D.E. Culler

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Memory consistency and event ordering in scalable shared-memory multiprocessors

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture ◽

10.1109/isca.1990.134503 ◽

2002 ◽

Cited By ~ 267

Author(s):

K. Gharachorloo ◽

D. Lenoski ◽

J. Laudon ◽

P. Gibbons ◽

A. Gupta ◽

...

Keyword(s):

Shared Memory ◽

Memory Consistency ◽

Shared Memory Multiprocessors ◽

Event Ordering

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A distributed I/O architecture for HARTS

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture ◽

10.1109/isca.1990.134543 ◽

2002 ◽

Cited By ~ 2

Author(s):

K.G. Shin ◽

G. Dykema

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A new approach to fast control of r/sup 2/r/sup 2/ 3-stage Benes networks of rr crossbar switches

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture ◽

10.1109/isca.1990.134507 ◽

2002 ◽

Cited By ~ 4

Author(s):

A. Youssef ◽

B. Arden

Keyword(s):

New Approach ◽

Crossbar Switches ◽

Fast Control ◽

Benes Networks

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[1990] Proceedings. The 17th Annual International Symposium on Computer ArchitectureLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc. Press

Maximizing performance in a striped disk array

Adaptive software cache management for distributed shared memory architectures

The TLB slice-a low-cost high-speed address translation mechanism

Boosting beyond static scheduling in a superscalar processor

The directory-based cache coherence protocol for the DASH multiprocessor

PLUS: a distributed shared-memory system

Monsoon: an explicit token-store architecture

Memory consistency and event ordering in scalable shared-memory multiprocessors

A distributed I/O architecture for HARTS

A new approach to fast control of r/sup 2/*r/sup 2/ 3-stage Benes networks of r*r crossbar switches

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture
Latest Publications

A new approach to fast control of r/sup 2/r/sup 2/ 3-stage Benes networks of rr crossbar switches