2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)
Latest Publications

TOTAL DOCUMENTS

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

9781467361736

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Wireless on Networks-on-Chip

2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) ◽

10.1109/slip.2013.6681675 ◽

2013 ◽

Author(s):

Baris Taskin

Keyword(s):

Networks On Chip ◽

On Chip

Download Full-text

Copyright page

2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) ◽

10.1109/slip.2013.6681689 ◽

2013 ◽

Download Full-text

Authors index

2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) ◽

10.1109/slip.2013.6681688 ◽

2013 ◽

Download Full-text

High-dimensional metamodeling for prediction of clock tree synthesis outcomes

2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) ◽

10.1109/slip.2013.6681685 ◽

2013 ◽

Cited By ~ 6

Author(s):

Andrew B. Kahng ◽

Bill Lin ◽

Siddhartha Nath

Keyword(s):

High Dimensional ◽

Clock Tree ◽

Clock Tree Synthesis ◽

Tree Synthesis

Download Full-text

LumiNOC: A low-latency, high-bandwidth per Watt, photonic Network-on-Chip

2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) ◽

10.1109/slip.2013.6681679 ◽

2013 ◽

Author(s):

Mark Browning ◽

Cheng Li ◽

Paul V. Gratz ◽

Samuel Palermo

Keyword(s):

Network On Chip ◽

Low Latency ◽

Photonic Network ◽

High Bandwidth ◽

On Chip

Download Full-text

Learning-based approximation of interconnect delay and slew in signoff timing tools

2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) ◽

10.1109/slip.2013.6681682 ◽

2013 ◽

Cited By ~ 7

Author(s):

Andrew B. Kahng ◽

Seokhyeong Kang ◽

Hyein Lee ◽

Siddhartha Nath ◽

Jyoti Wadhwani

Keyword(s):

Interconnect Delay

Download Full-text

2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) ◽

10.1109/slip.2013.6681690 ◽

2013 ◽

Download Full-text

Worst-case noise prediction using power network impedance profile

2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) ◽

10.1109/slip.2013.6681681 ◽

2013 ◽

Cited By ~ 4

Author(s):

Xiang Zhang ◽

Yang Liu ◽

Chung-Kuan Cheng

Keyword(s):

Noise Prediction ◽

Power Network ◽

Worst Case ◽

Impedance Profile

Download Full-text

Chip-scale physical interconnect models (Tutorial)

2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) ◽

10.1109/slip.2013.6681684 ◽

2013 ◽

Author(s):

Rasit O. Topaloglu

Download Full-text

Performance modeling for interconnects for conventional and emerging switches

2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) ◽

10.1109/slip.2013.6681683 ◽

2013 ◽

Author(s):

Shaloo Rakheja ◽

Vachan Kumar ◽

Azad Naeemi

Keyword(s):

Performance Modeling

Download Full-text

2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Wireless on Networks-on-Chip

Copyright page

Authors index

High-dimensional metamodeling for prediction of clock tree synthesis outcomes

LumiNOC: A low-latency, high-bandwidth per Watt, photonic Network-on-Chip

Learning-based approximation of interconnect delay and slew in signoff timing tools

Table of contents

Worst-case noise prediction using power network impedance profile

Chip-scale physical interconnect models (Tutorial)

Performance modeling for interconnects for conventional and emerging switches

Export Citation Format

2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Wireless on Networks-on-Chip

Copyright page

Authors index

High-dimensional metamodeling for prediction of clock tree synthesis outcomes

LumiNOC: A low-latency, high-bandwidth per Watt, photonic Network-on-Chip

Learning-based approximation of interconnect delay and slew in signoff timing tools

Table of contents

Worst-case noise prediction using power network impedance profile

Chip-scale physical interconnect models (Tutorial)

Performance modeling for interconnects for conventional and emerging switches

2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)
Latest Publications