Sol–gel deposited xerogel, aerogel and porogen based porous low-k thin films: A comparative investigation

Low dielectric constant (Low-[Formula: see text]) films are used as inter layer dielectric (ILD) in nanoelectronic devices to reduce interconnect delay, crosstalk noise and power consumption. Tailoring capability of porous low-[Formula: see text] films attracted more attention. Present work investigates comparative study of xerogel, aerogel and porogen based porous low-[Formula: see text] films. Deposition of SiO2 and incorporation of less polar bonds in film matrix is confirmed using Fourier Transform Infra-Red Spectroscopy (FTIR). Refractive indices (RI) of xerogel, aerogel and porogen based low-[Formula: see text] films observed to be as low as 1.25, 1.19 and 1.14, respectively. Higher porosity percentage of 69.46% is observed for porogen-based films while for shrinked xerogel films, it is lowered to 45.47%. Porous structure of low-[Formula: see text] films has been validated by using Field Emission Scanning Electron Microscopy (FE-SEM). The pore diameters of porogen based annealed samples were in the range of 3.53–25.50 nm. The dielectric constant ([Formula: see text]) obtained from RI for xerogel, aerogel and porogen based films are 2.58, 2.20 and 1.88, respectively.

Memory and I/O optimized rectilinear steiner minimum tree routing for VLSI

As the size of devices are scaling down at rapid pace, the interconnect delay play a major part in performance of IC chips. Therefore minimizing delay and wire length is the most desired objective. FLUTE (Fast Look-Up table) presented a fast and accurate RSMT (Rectilinear Steiner Minimum Tree) construction for both smaller and higher degree net. FLUTE presented an optimization technique that reduces time complexity for RSMT construction for both smaller and larger degree nets. However for larger degree net this technique induces memory overhead, as it does not consider the memory requirement in constructing RSMT. Since availability of memory is very less and is expensive, it is desired to utilize memory more efficiently which in turn results in reducing I/O time (i.e. reduce the number of I/O disk access). The proposed work presents a Memory Optimized RSMT (MORSMT) construction in order to address the memory overhead for larger degree net. The depth-first search and divide and conquer approach is adopted to build a Memory optimized tree. Experiments are conducted to evaluate the performance of proposed approach over existing model for varied benchmarks in terms of computation time, memory overhead and wire length. The experimental results show that the proposed model is scalable and efficient.

Memory and I/O Optimized Rectilinear Steiner Minimum Tree Routing For VLSI

As the size of devices are scaling down at rapid pace, the interconnect delay play a major part in performance of IC chips. Therefore minimizing delay and wire length is the most desired objective. FLUTE (Fast Look-Up table) presented a fast and accurate RSMT (Rectilinear Steiner Minimum Tree) construction for both smaller and higher degree net. In this paper, FLUTE presented an optimization technique that reduces time complexity for RSMT construction for both smaller and larger degree nets. However for larger degree net this technique induces memory overhead, as it does not consider the memory requirement in constructing RSMT. Since availability of memory is very less and is expensive, it is desired to utilize memory more efficiently which in turn results in reducing I/O time (i.e. reduce the number of I/O disk access). The proposed work presents a Memory Optimized RSMT (MORSMT) construction in order to address the memory overhead for larger degree net. The depth-first search and divide and conquer approach is adopted to build a Memory optimized tree. Experiments are conducted to evaluate the performance of proposed approach over existing model for varied benchmarks in term of computation time, memory overhead and wire length. The experimental results show that the proposed model is scalable and efficient.

DESIGN AND EFFICIENCY ANALYSIS OF NANOCARBON INTERCONNECT STRUCTURES

With significant reduction in the size of ICs, there has been a massive increase in the operating speed. Due to this condition, the area available for interconnects within the transistor and between transistors in an IC is greatly reduced. Carbon wires pose high resistance and power dissipation in constrained space. It is necessary to opt efficient means to overcome this issue. The drawbacks of traditional metallic interconnects are overcome by nanocarbon interconnects. Considering factors such as shrinking dimensions, interconnect delay and power dissipation, we have considered four nanocarbon interconnect structures for analysis in this paper. The design and efficiency are analysed for Graphene Nanoribbon (GNR), Carbon Nanotube, Cu-Nanocarbon and All Carbon 3-D interconnects.

Research on Net Weighting Schemes in Performance Driven Global Routing

In today’s VLSI technology nodes, interconnect delay plays an important part in deciding the performance of the chip designs. Various methods are introduced at the level of placement and routing to address this problem. To address this problem at the level of global routing, net weighting methods are being explored in the industry and academia. We investigate four methods for weighting the critical nets during performance driven global routing. This paper presents a comparative study conducted on the four methods for net weighting proposed by us in our previous works

Stochastic Delay Characterization for Multicoupled RLC Interconnects Under Process Variations

The characterization of interconnect delay metrics in terms of process variations is an important but complicated task for statistical timing analysis in today’s integrated circuits (ICs). This paper presents a stochastic delay characterization framework for multicoupled interconnects in the presence of process variation. The proposed method starts with deriving the stochastic nodal equations for the RLC network that models multicoupled interconnects. By employing polynomial chaos (PC) expansion, a nonsampling-based stochastic prediction method, we further represent the voltage responses of network nodes as a series of orthogonal polynomials of random variables. During the expansion procedure, we use an adaptive approximation algorithm to reduce the number of required sampling points. We then use a stochastic collocation method to estimate the coefficients in the PC expansion model. With the voltage response determined as an expression of a multi-dimensional polynomial of random variables, the stochastic properties of the delay of multicoupled interconnects can be predicted. The proposed method not only takes into account the strong correlations among process variations, but also extracts an explicit delay representation for multicoupled interconnects in terms of process variations. Experimental results demonstrate that the delay characteristics predicted by the proposed method match well with the results by the brute-force Monte-Carlo method. Moreover, a significant speedup over the Monte-Carlo method has been achieved by the proposed delay characterization framework.

Delay Approximation Model for Prime Speed Interconnects in Current Mode

There is enormous demand for high speed VLSI networks in present days. The coupling capacitance and interconnect delay play a major role in judging the behavior of on chip interconnects. There is an on chip inductance effect as we switch to low technology that leads to delay in interconnecting. In this paper we are attempting to apply second order transfer function designed with finite difference equation and transform Laplace at the ends of the source and load termination. Analysis shows that the current signaling mode in VLSI interconnects provide better time delay than the voltage mode