Transactions on High-Performance Embedded Architectures and Compilers III - Lecture Notes in Computer Science
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Published By Springer Berlin Heidelberg

9783642194474, 9783642194481

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A Multithreaded Multicore System for Embedded Media Processing

Transactions on High-Performance Embedded Architectures and Compilers III - Lecture Notes in Computer Science ◽

10.1007/978-3-642-19448-1_9 ◽

2011 ◽

pp. 154-173 ◽

Cited By ~ 10

Author(s):

Jan Hoogerbrugge ◽

Andrei Terechko

Keyword(s):

Media Processing ◽

Multicore System

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Exploring the Architecture of a Stream Register-Based Snoop Filter

Transactions on High-Performance Embedded Architectures and Compilers III - Lecture Notes in Computer Science ◽

10.1007/978-3-642-19448-1_6 ◽

2011 ◽

pp. 93-114 ◽

Cited By ~ 3

Author(s):

Matthias Blumrich ◽

Valentina Salapura ◽

Alan Gara

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Software-Level Instruction-Cache Leakage Reduction Using Value-Dependence of SRAM Leakage in Nanometer Technologies

Transactions on High-Performance Embedded Architectures and Compilers III - Lecture Notes in Computer Science ◽

10.1007/978-3-642-19448-1_15 ◽

2011 ◽

pp. 275-299

Author(s):

Maziar Goudarzi ◽

Tohru Ishihara ◽

Hamid Noori

Keyword(s):

Instruction Cache ◽

Leakage Reduction

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Constructing Application-Specific Memory Hierarchies on FPGAs

Transactions on High-Performance Embedded Architectures and Compilers III - Lecture Notes in Computer Science ◽

10.1007/978-3-642-19448-1_11 ◽

2011 ◽

pp. 201-216 ◽

Cited By ~ 1

Author(s):

Harald Devos ◽

Jan Van Campenhout ◽

Ingrid Verbauwhede ◽

Dirk Stroobandt

Keyword(s):

Memory Hierarchies ◽

Specific Memory ◽

Application Specific

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Cache Sensitive Code Arrangement for Virtual Machine

Transactions on High-Performance Embedded Architectures and Compilers III - Lecture Notes in Computer Science ◽

10.1007/978-3-642-19448-1_2 ◽

2011 ◽

pp. 24-42

Author(s):

Chun-Chieh Lin ◽

Chuen-Liang Chen

Keyword(s):

Virtual Machine

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Power-Aware Dynamic Cache Partitioning for CMPs

Transactions on High-Performance Embedded Architectures and Compilers III - Lecture Notes in Computer Science ◽

10.1007/978-3-642-19448-1_8 ◽

2011 ◽

pp. 135-153 ◽

Cited By ~ 11

Author(s):

Isao Kotera ◽

Kenta Abe ◽

Ryusuke Egawa ◽

Hiroyuki Takizawa ◽

Hiroaki Kobayashi

Keyword(s):

Cache Partitioning ◽

Dynamic Cache Partitioning

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Eighth MEDEA Workshop

Transactions on High-Performance Embedded Architectures and Compilers III - Lecture Notes in Computer Science ◽

10.1007/978-3-642-19448-1_5 ◽

2011 ◽

pp. 91-92

Author(s):

Sandro Bartolini ◽

Pierfrancesco Foglia ◽

Cosimo Antonia Prete

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Improving Branch Prediction by Considering Affectors and Affectees Correlations

Transactions on High-Performance Embedded Architectures and Compilers III - Lecture Notes in Computer Science ◽

10.1007/978-3-642-19448-1_4 ◽

2011 ◽

pp. 69-88

Author(s):

Yiannakis Sazeides ◽

Andreas Moustakas ◽

Kypros Constantinides ◽

Marios Kleanthous

Keyword(s):

Branch Prediction

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Data Layout for Cache Performance on a Multithreaded Architecture

Transactions on High-Performance Embedded Architectures and Compilers III - Lecture Notes in Computer Science ◽

10.1007/978-3-642-19448-1_3 ◽

2011 ◽

pp. 43-68 ◽

Cited By ~ 1

Author(s):

Subhradyuti Sarkar ◽

Dean M. Tullsen

Keyword(s):

Data Layout ◽

Cache Performance ◽

Multithreaded Architecture

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Robust Adaptation to Available Parallelism in Transactional Memory Applications

Transactions on High-Performance Embedded Architectures and Compilers III - Lecture Notes in Computer Science ◽

10.1007/978-3-642-19448-1_13 ◽

2011 ◽

pp. 236-255 ◽

Cited By ~ 1

Author(s):

Mohammad Ansari ◽

Mikel Luján ◽

Christos Kotselidis ◽

Kim Jarvis ◽

Chris Kirkham ◽

...

Keyword(s):

Transactional Memory ◽

Memory Applications

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Transactions on High-Performance Embedded Architectures and Compilers III - Lecture Notes in Computer ScienceLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By Springer Berlin Heidelberg

A Multithreaded Multicore System for Embedded Media Processing

Exploring the Architecture of a Stream Register-Based Snoop Filter

Software-Level Instruction-Cache Leakage Reduction Using Value-Dependence of SRAM Leakage in Nanometer Technologies

Constructing Application-Specific Memory Hierarchies on FPGAs

Cache Sensitive Code Arrangement for Virtual Machine

Power-Aware Dynamic Cache Partitioning for CMPs

Eighth MEDEA Workshop

Improving Branch Prediction by Considering Affectors and Affectees Correlations

Data Layout for Cache Performance on a Multithreaded Architecture

Robust Adaptation to Available Parallelism in Transactional Memory Applications

Transactions on High-Performance Embedded Architectures and Compilers III - Lecture Notes in Computer Science
Latest Publications