Design and Assertion Based Verification of RISC-V Processor Subsystems

RISC-V is an open, free standard architecture. As its open-source architecture, it can be used in multiple applications like embedded processors, IoT, artificial intelligence, machine learning, military and defense applications. The parameters like throughput, performance, high speed etc., become essential in designing processor architecture. Pipelining is one such unique feature supported by RISC-V ISA, which basically involves the execution of multiple instructions in single cycle. This feature helps in improving the performance of the processor architecture. RISC-V ISA supports five stages of pipelining they are instruction fetch, instruction decode, execute, memory and write-back stage. The work covered in this paper involves the design and implementation of the subsystems of the RISC-V ISA which are present in different stages of pipeline architecture. The subsystems included in this work are Floating Point Unit (FPU) of Execute stage, Branch Prediction Unit (BPU) of instruction fetch stage, Forwarding Unit of execution stage, Operand Logic of decode stage and Floating-Point register file of Write-back stage. These subsystems are designed using Verilog Hardware Description Language in Xilinx ISE. Followed by the implementation the verification of the floating-point unit and the forwarding unit is performed using System Verilog Assertions in QuestaSim. The Assertion coverage report for the same is extracted.

Autistic Savants and Mathematical sequence prediction.

In the third paper in a series of papers on autism savants, detection of giftedness and the use of mental arithmetic as an intervention in autism and a practice of metal wellness, we describe the use of python scripts towards primality detection exercises, of both small primes and arbitrary sized numbers and several other exercises including sequence prediction, inspired by branch prediction architectures. Sequence prediction as a mental exercise, is used as infotainment and as a wellness exercise, and a possible intervention in ASD. Several prediction mechanisms inspired by data and prediction algorithms are described. Keywords: ASD, Autism Savants, Education For The Gifted, primality detection, data mining, basket of associations, sequences, branch prediction, plotting graphs.

Towards the Improving Branch Instructions Identification in High- Performance Processors: Issues, Challenges and Techniques

Introduction: Accurate branch prediction technique has become compulsory in the superscalar and deep pipeline processors. The conditional instructions can break the continuous flow of execution in the pipeline stages, thereby decreasing processor performance. Discussion: This paper highlights the concept of branch prediction, some issues and challenges, and techniques for improving processor performance. Further, this paper also presents the role of branch prediction in different processors and their features. Conclusion: The concept of the branch prediction used in parallel processors to enhance the execution speed of the conditional branch instructions and improve the processor's performance is highlighted in this paper. Further, this paper highlights the branch predictor techniques with their features and presents the challenges, issues, and future techniques related to the branch prediction.