Optimizing the Potential Impact of Energy Recovery and Pipe Replacement on Leakage Reduction in a Medium Sized District Metered Area

The drive for sustainable societies with more resilient infrastructure networks has catalyzed interest in leakage reduction as a subsequent benefit to energy recovery in water distribution systems. Several researchers have conducted studies and piloted successful energy recovery installations in water distribution systems globally. Challenges remain in the determination of the number, location, and optimal control setting of energy recovery devices. The PERRL 2.0 procedure was developed, employing a genetic algorithm through extended period simulations, to identify and optimize the location and size of hydro-turbine installations for energy recovery. This procedure was applied to the water supply system of the town of Stellenbosch, South Africa. Several suitable locations for pressure reduction, with energy recovery installations between 600 and 800 kWh/day were identified, with the potential to also reduce leakage in the system by 2 to 4%. Coupling the energy recovery installations with a pipe replacement model showed a further reduction in leakage up to a total of above 6% when replacing 10% of the aged pipes within the network. Several solutions were identified on the main supply line and the addition of a basic water balance, to the analysis, was found valuable in preliminarily evaluation and identification of the more sustainable solutions.

Comprehensive Analysis of SRAM Cell Architectures With 18nm FinFET for Low Power Applications

The SRAM cells are used in many applications where power consumption will be the main constraint. The Conventional 6T SRAM cell has reduced stability and more power consumption when technology is scaled resulting in supply voltage scaling, so other alternative SRAM cells from 7T to 12T have been proposed which can address these problems. Here a low power 7T SRAM cell is suggested which has low power consumption and condensed leakage currents and power dissipation. The projected design has a leakage power of 5.31nW and leakage current of 7.58nA which is 84.9% less than the 7T SRAM cell without using the proposed leakage reduction technique and it is 22.4% better than 6T SRAM and 22.1% better than 8T SRAM cell when both use the same leakage reduction technique. The cell area of the 7T SRAM cell is 1.25µM2, 6T SRAM is 1.079µM2 and that of 8T SRAM is 1.28µM2all the results are simulated in cadence virtuoso using 18nm technology.

Leakage Power Reduction in CMOS VLSI Circuits using Advance Leakage Reduction Method

Recently, consumption of power is key problem of logic circuits based on Very Large Scale Integration. More potentiality consumption isn’t considered an appropriate for storage cell life for the use in cell operations and changes parameters such as optimality, efficiency etc, more consumption of power also provides for minimization of cell storage cycle. In present scenario static consumption of power is major troubles in logic circuits based on CMOS. Layout of drainage less circuit is typically complex. Several derived methods for minimization of consumption of potentiality for logic circuits based on CMOS. For this research paper, a technique called Advance Leakage reduction (AL reduction) is proposed to reduce the leakage power in CMOS logic circuits. To draw our structure circuit related to CMOS like Inverter, inverted AND, and NOR etc. we have seen the power and delay for circuits. This paper incorporates, analyzing of several minimization techniques as compared with proposed work to illustrate minimization in ratio of energy and time usage and time duration for propagation. LECTOR, Source biasing, Stack ONOFIC method is observed and analyzed with the proposed method to evaluate the leakage power consumption and propagation delay for logic circuits based on CMOS. Entire work has done in LT Spice Software with 180nm library of CMOS.